Abstract: An image sensor cell, wherein at least one of a plurality of transistors included in image sensor cell is a recess transistor having a channel region recessed into a substrate. The image sensor cell includes an image charge generating unit for generating an image charge corresponding to an image signal, and an image charge converting unit for converting the image charge into an electrical signal, wherein at least one of a plurality of transistors included in the image charge converting unit is a recess transistor including a channel region that is recessed into a substrate.

Abstract: Disclosed are a porous electroformed shell for forming a grain pattern and a manufacturing method thereof. The method includes the step of implanting a fiber into a patterned surface of a negative-type silicone cast; applying, laminating, and curing an epoxy resin on the patterned surface of the negative-type silicone cast, and transferring the fiber from the negative-type silicone cast to an epoxy mandrel during demolding of the epoxy mandrel; forming a conductive thin film on the patterned surface of the epoxy mandrel, and causing the patterned surface to be conductive; removing the fiber having the conductive thin film from a surface of the epoxy mandrel; forming an electrodeposited layer by electrodepositing an electroforming metal on the conductive thin film while generating and growing a fine pore at a position of a hole due to the removal of the fiber; and demolding the electrodeposited layer having the fine pore from the epoxy mandrel.

Abstract: A method of checking a sealing state of a housing includes starting an operation of a pressure sensor configured to measure an internal pressure of the housing. The method includes checking whether or not the housing is pressed. The method further includes checking the sealing state of the housing through checking a measured value of the pressure sensor under a pressure of the housing. An apparatus for checking a sealing state of a housing includes the housing configured to keep an internal space thereof sealed off from an outside, a pressure sensor configured to measure a pressure of the internal space, and an interface unit configured to provide to the pressure sensor a control signal that controls an operation of the pressure sensor, and provide pressure information detected through the pressure sensor.

Abstract: Provided is an organic pixel, which includes a semiconductor substrate including a pixel circuit, an interconnection layer having a first contact and a first electrode formed on a semiconductor substrate, and an organic photo-diode formed on the interconnection layer. For example, the organic photo-diode includes an insulation layer formed on the first electrode, a second electrode and a photo-electric conversion region formed between the first contact, the insulation layer and the second electrode. The photo-electric conversion region includes an electron donating organic material and an electron accepting organic material. The organic photo-diode may further include a second contact electrically connected to the first contact. The horizontal distance between the second contacts and the insulation layer may be less than or equal to a few micrometers, for example, 10 micrometers.

Abstract: A method of manufacturing a flexible printed circuit board including determining an elastic modulus of a conductive portion and an elastic modulus of first and second dielectric portions, determining a thickness of the conductive portion and the first and second dielectric portions so that a neutral plane is located within a predetermined range of the thickness of the conductive portion, the neutral plane being substantially free from tension or compression in response to bending of the flexible printed circuit board, and insulating the conductive portion according to the determined thickness and the determined elastic modulus.

Abstract: A pedestal level compensation method includes calculating a dark level difference error depending on temperature, calculating a pedestal level offset depending on an analog gain, and compensating a pedestal level according to the dark level difference error and the pedestal level offset.

Abstract: Disclosed herein are a system for measuring a warpage and a method for measuring a warpage. The system for measuring a warpage includes: a heating plate portion heating the sample; and a reference gating portion disposed between the sample and the camera so as to be spaced apart from the sample by a predetermined distance, wherein the reference grating portion includes a plurality of wires that are each spaced apart from each other by a predetermined interval, thereby accurately measuring the warpage without being affected by the fume generated from the sample.

Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.

Abstract: Disclosed herein is a lamination layer type semiconductor package, and more particularly, a lamination layer type semiconductor package capable of maintaining a thickness of a package on package structure at a minimum and minimizing a warpage defect by mounting two chips so as to correspond to each other. The lamination layer type semiconductor package includes: an upper package having an upper flip chip mounted on an upper substrate; a lower package having a lower flip chip mounted on a lower substrate and disposed so as to closely adhere the upper flip chip and the lower flip chip to each other; a heat dissipation adhesive member adhesively fixing the upper flip chip and the lower flip chip and dissipating heat generated from the upper flip chip and the lower flip chip; and a molding member molding between the upper substrate and the lower substrate.

Abstract: Disclosed herein are an electronic component package and a method of manufacturing the same. The electronic component package includes: a substrate; a connection member provided on at least one surface of the substrate; an active element coupled to the substrate by the connection member; and a molding part covering an exposed surface of the active element, wherein the molding part is formed of a first material having a coefficient of thermal expansion of 8 to 15 ppm/° C. and thermal conductivity of 1 to 5 W/m° C. Therefore, warpage may be significantly decreased and heat radiation performance of the active element may be improved, as compared with the case of implementing the molding part using an EMC according to the related art.

Abstract: Disclosed herein is an electronic component package including: a connection member provided on at least one surface of a substrate; an active element coupled to the substrate by the connection member; a molding part covering an exposed surface of the active element; and an additional layer formed on an exposed surface of the molding part to decrease a warpage phenomenon. In the electronic component package, the warpage phenomenon may be decreased as compared with the related art.

Abstract: There is provided an In nanowire including a substrate, an indium thin film formed on the substrate, an insulating film formed on the indium thin film and having at least one through hole through formation of a pattern, and an In nanowire vertically protruded from the indium thin film through the at least one through hole.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.

Abstract: Disclosed herein are a system of measuring a warpage and a method of measuring a warpage. The system of measuring a warpage of a sample by analyzing an image photographed by the camera using light that is diffused from a light source and reflected on a surface of a sample and is arrived at the camera through a reference grating part, the system includes: an intake part that removes a fume generated from the sample. By this configuration, it is possible to measure the warpage while effectively removing the fume generated from the sample according to the increase in the temperature of the sample at the time of measuring the warpage, thereby improving the accuracy of the warpage measurement.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.

Abstract: There is provided a linear vibrator, including: a fixed part providing an interior space having a predetermined size; at least one magnet disposed in the interior space and generating magnetic force; a vibration part including a coil facing the magnet and generating electromagnetic force through interaction with the magnet and a mass body; and an elastic member coupled to the fixed part and the vibration part to mediate vibrations of the vibration part and having a damping increasing portion attached to a predetermined region of a surface thereof.

Abstract: Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package.

Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.

Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.