Patents by Inventor Kyung-Rae Byun

Kyung-Rae Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11670657
    Abstract: An image sensor includes; a photoelectric conversion element disposed on a substrate, a fence structure disposed on the substrate and including a low refractive index layer stacked on a barrier layer, wherein the barrier layer includes at least one metal, and a color filter disposed inwardly lateral with respect to a sidewall of the fence structure, wherein the barrier layer includes an inward lateral protrusion.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 6, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Hwan Jeon, Doo Won Kwon, Chan Ho Park, Kyung Rae Byun, Dong-Chul Lee, Chong Kwang Chang
  • Publication number: 20230064084
    Abstract: An image sensor including: a semiconductor substrate including a plurality of pixel regions; an anti-reflection layer on the semiconductor substrate; color filters provided on the anti-reflection layer and in the pixel regions; and a fence structure disposed between adjacent ones of the color filters, wherein the fence structure includes: a lower portion penetrating the anti-reflection layer; an upper portion on the anti-reflection layer; and an intermediate portion between the lower portion and the upper portion, wherein the fence structure has undercut regions, which are provided at both sides of the intermediate portion and are between the upper portion of the fence structure and a top surface of the anti-reflection layer.
    Type: Application
    Filed: July 18, 2022
    Publication date: March 2, 2023
    Inventors: MINHWAN JEON, Chanho Park, Kyung Rae Byun, Chang Kyu Lee, Chongkwang Chang
  • Patent number: 11508775
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Shi Li Quan, Hyung-yong Kim, Seug-gab Park, In-gyu Baek, Kyung-rae Byun, Jin-yong Choi
  • Publication number: 20210366974
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gang ZHANG, Shi Li QUAN, Hyung-yong KIM, Seug-gab PARK, In-gyu BAEK, Kyung-rae BYUN, Jin-yong CHOI
  • Patent number: 11183527
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Shi Li Quan, Hyung-yong Kim, Seug-gab Park, In-gyu Baek, Kyung-rae Byun, Jin-yong Choi
  • Publication number: 20210126028
    Abstract: An image sensor includes; a photoelectric conversion element disposed on a substrate, a fence structure disposed on the substrate and including a low refractive index layer stacked on a barrier layer, wherein the barrier layer includes at least one metal, and a color filter disposed inwardly lateral with respect to a sidewall of the fence structure, wherein the barrier layer includes an inward lateral protrusion.
    Type: Application
    Filed: August 26, 2020
    Publication date: April 29, 2021
    Inventors: MIN HWAN JEON, DOO WON KWON, CHAN HO PARK, KYUNG RAE BYUN, DONG-CHUL LEE, CHONG KWANG CHANG
  • Patent number: 10784314
    Abstract: The present invention relates to image sensors and method of manufacturing the same. The image sensor may include a substrate having pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer surrounding the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; a color filter filling the trench; a protective film exposing the upper contact via; a first transparent electrode on the protective film that contacts the upper contact via; and an organic photoelectric layer on the first transparent electrode.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Hyun Yoo, Eun Mi Kim, Joon Kim, Chang Hwa Kim, Sang Su Park, Kyung Rae Byun, Sang Hoon Song
  • Publication number: 20200127034
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Application
    Filed: May 13, 2019
    Publication date: April 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gang ZHANG, Shi Li QUAN, Hyung-yong KIM, Seug-gab PARK, ln-gyu BAEK, Kyung-rae BYUN, Jin-yong CHOI
  • Publication number: 20190386065
    Abstract: The present invention relates to image sensors and method of manufacturing the same. The image sensor may include a substrate having pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer surrounding the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; a color filter filling the trench; a protective film exposing the upper contact via; a first transparent electrode on the protective film that contacts the upper contact via; and an organic photoelectric layer on the first transparent electrode.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Inventors: Jong Hyun YOO, Eun Mi KIM, Joon KIM, Chang Hwa KIM, Sang Su PARK, Kyung Rae BYUN, Sang Hoon SONG
  • Patent number: 10446611
    Abstract: An image sensor may include a substrate having a plurality of pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the plurality of pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer to surround the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; and a color filter filling the trench. A protective film exposing the upper contact via, a first transparent electrode on the protective film and in contact with the upper contact via, and an organic photoelectric layer formed on the first transparent electrode may be provided.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Hyun Yoo, Eun Mi Kim, Joon Kim, Chang Hwa Kim, Sang Su Park, Kyung Rae Byun, Sang Hoon Song
  • Publication number: 20190252466
    Abstract: An image sensor may include a substrate having a plurality of pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the plurality of pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer to surround the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; and a color filter filling the trench. A protective film exposing the upper contact via, a first transparent electrode on the protective film and in contact with the upper contact via, and an organic photoelectric layer formed on the first transparent electrode may be provided.
    Type: Application
    Filed: August 23, 2018
    Publication date: August 15, 2019
    Inventors: Jong Hyun YOO, Eun Mi KIM, Joon KIM, Chang Hwa KIM, Sang Su PARK, Kyung Rae BYUN, Sang Hoon SONG
  • Patent number: 9679943
    Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Chul Park, Shin Jae Kang, Shin Kwon, Kyung Rae Byun
  • Patent number: 9647201
    Abstract: The inventive concepts provide magnetic memory devices. The device includes a first magnetic pattern provided in one united body on a substrate and having a plurality of through-holes, a plurality of second magnetic patterns spaced apart from each other on the first magnetic pattern, a tunnel barrier between the first magnetic pattern and the second magnetic patterns, top electrodes disposed on the second magnetic patterns, respectively, and a plurality of plugs electrically connecting the top electrodes to the substrate through the through-holes, respectively.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Kyung Rae Byun
  • Patent number: 9634240
    Abstract: Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Byoungjae Bae, Shin-Jae Kang, Eunsun Noh, Kyung Rae Byun
  • Publication number: 20160104745
    Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.
    Type: Application
    Filed: May 13, 2015
    Publication date: April 14, 2016
    Inventors: Jong Chul PARK, Shin Jae KANG, Shin KWON, Kyung Rae BYUN
  • Publication number: 20160093799
    Abstract: The inventive concepts provide magnetic memory devices. The device includes a first magnetic pattern provided in one united body on a substrate and having a plurality of through-holes, a plurality of second magnetic patterns spaced apart from each other on the first magnetic pattern, a tunnel barrier between the first magnetic pattern and the second magnetic patterns, top electrodes disposed on the second magnetic patterns, respectively, and a plurality of plugs electrically connecting the top electrodes to the substrate through the through-holes, respectively.
    Type: Application
    Filed: June 3, 2015
    Publication date: March 31, 2016
    Inventors: Jongchul PARK, Kyung Rae BYUN
  • Publication number: 20150287907
    Abstract: Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.
    Type: Application
    Filed: December 11, 2014
    Publication date: October 8, 2015
    Inventors: Jongchul PARK, Byoungjae BAE, Shin-Jae KANG, Eunsun NOH, Kyung Rae BYUN
  • Patent number: 8236682
    Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Rae Byun, Suk-Ho Joo, Min-Joon Park
  • Patent number: 7982318
    Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: July 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Eun Heo, Young-Moon Choi, Sun-Woo Lee, Hong-Sik Yoon, Kyung-Rae Byun
  • Publication number: 20100264544
    Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.
    Type: Application
    Filed: January 19, 2007
    Publication date: October 21, 2010
    Inventors: Jang-Eun Heo, Young-Moon Choi, Sun-Woo Lee, Hong-Sik Yoon, Kyung-Rae Byun