Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.

Abstract: The present disclosure relates to an apparatus for fabricating a display panel including: an attachment member having a fixing portion in a pressurization direction to which a pressurization header is fixed, an attachment driving member configured to move the attachment member and the pressurization header in the pressurization direction or a detachment direction through a fixing frame of the attachment member, a first pressure sensing module between the pressurization header and the attachment member and configured to generate first pressure detection signals according to pressure applied to the pressurization header, a gradient setting module configured to set a gradient of the pressurization header based on magnitudes of the first pressure detection signals, and a gradient control module configured to adjust gradients of the pressurization header, the attachment member, and the fixing frame according to control of the gradient setting module.

Abstract: Disclosed herein is a wearable device for body correction, which is capable of adapting a position suitable for pressing a patient's body's curve to be corrected. To this end, the wearable device for body correction includes an outerwear worn on an upper body of a patient, a curve presser disposed on the outerwear and configured to press a curve of the body to be corrected, a strength adjuster disposed on the outerwear, connected to the curve presser by a wire, and configured to adjust a strength of pressure applied by the curve presser by adjusting an amount of winding/unwinding of the wire, and a guide rail disposed on the outerwear and configured to guide vertical sliding of at least one of the curve presser and the strength adjuster.

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: The present invention provides methods for treating or ameliorating metabolic diseases, cholestatic liver diseases, or organ fibrosis, which comprises administering to a subject a therapeutically effective amount of a pharmaceutical composition comprising an isoxazole derivative, a racemate, an enantiomer, or a diastereoisomer thereof, or a pharmaceutically acceptable salt of the derivative, the racemate, the enantiomer, or the diastereoisomer.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: An operating device and method for remotely controlling an arming device. The method includes confirming a tracking image at each firing time point of a laser beam transmitted by the range finder; based on an image correlation value of a target locked on by a tracking gate in the tracking image exceeding a threshold value, determining that the target is normally locked on; determining whether the laser beam from the range finder hits the target determined as being normally locked on based on a center value of the tracking image and a center value of the tracking gate; and based on the laser beam from the range finder hitting the target normally locked on, determining a range measurement value measured by the range finder as a true value of the target and determining other range measurement values as wrong measurement values.

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

Abstract: Proposed is an apparatus for operating a syringe. The apparatus includes a body in which a syringe filled with one or more fluids is mounted, an actuator disposed behind the body and configured to selectively discharge the one or more fluid filled in the syringe by moving forward and backward a piston, and a holder provided on a bottom of the body, configured to hold a finger or the back of a hand of a user, and formed in a curved shape having a predetermined area to be able to be supported on the finger or the back of the hand of the user.

Abstract: Proposed is a system for operating a syringe. The system includes an apparatus for operating a syringe in which a syringe filled with one or more fluids is mounted and that includes a motor configured to selectively discharge the one or more fluids filled in the syringe by moving forward and backward a piston of the syringe, and a controller configured to control movement of the piston of the syringe through the motor, in which the controller moves the piston to follow a predetermined motion on the basis of a set mode when recognizing a request to operate or stop the apparatus for operating a syringe.

Abstract: Proposed is an apparatus for operating a syringe. The apparatus includes a body in which a syringe filled with one or more fluids is mounted, an actuator disposed behind the body and configured to selectively discharge the one or more fluid filled in the syringe by moving forward and backward a piston, and a cover having a shape surrounding a top of the syringe, hinged at a side to the body, and configured to cover the syringe mounted in the body by rotating through a hinge, thereby fixing the syringe with the body.

Abstract: A electronic device including a host connector and memory device is provided. The host connector includes a connector pin, and the memory connector includes a connection terminal electrically connected to the connector pin of the host connector. The connector pin includes a first conductor part including a conductor, a second conductor part including the conductor, the second conductor part being bent from the first conductor part in a direction towards the connection terminal, and a stub including an insulator, the stub being bent from the second conductor part in a direction away from the connection terminal. The connection terminal includes a first region including an insulator, and a second region including a conductor. The second conductor part is electrically connected to the second region, so that the host connector is electrically connected to the memory connector.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.