Abstract: A remote-controlled weapon system, mounted in a moving platform, includes at least one processor that implements: a first posture calculator that calculates a first pixel movement amount corresponding to a posture change amount of a camera during a time interval between a first image and a second image, received after the first image; a second posture calculator that calculates a second pixel movement amount corresponding to a control command for changing a posture of the camera to match a moving target, detected from the second image, with an aiming point; and a region of interest (ROI) controller that calculates a third pixel movement amount corresponding to vibration of the camera based on the first pixel movement amount and the second pixel movement amount, and estimate a location of an ROI that is to be set on the moving target of the second image, based on the third pixel movement amount.

Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

Abstract: A electronic device including a host connector and memory device is provided. The host connector includes a connector pin, and the memory connector includes a connection terminal electrically connected to the connector pin of the host connector. The connector pin includes a first conductor part including a conductor, a second conductor part including the conductor, the second conductor part being bent from the first conductor part in a direction towards the connection terminal, and a stub including an insulator, the stub being bent from the second conductor part in a direction away from the connection terminal. The connection terminal includes a first region including an insulator, and a second region including a conductor. The second conductor part is electrically connected to the second region, so that the host connector is electrically connected to the memory connector.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating an autoimmune disease, including stem cells treated with a protein kinase C activator or a culture thereof, and more specifically, the present invention relates to a pharmaceutical composition for preventing or treating an autoimmune disease, which can inhibit the function of B cells and have an excellent prophylactic or therapeutic effect for an autoimmune disease.

Abstract: A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.

Abstract: An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

Abstract: The present invention relates to a biomarker for prediction of proliferation and migration capacity of mesencymal stem cells and a use thereof, and more specifically, the present invention relates to a biomarker for prediction of proliferation or migration capacity of mesenchymal stem cells including peroxiredoxin 6 and a use thereof. According to the present invention, by measuring the expression level of the biomarker, the proliferation and migration capacity of mesenchymal stem cells can be predicted.

Abstract: A semiconductor package including a first package including a memory chip having a memory cell, and a capacitor structure disposed independently of the memory chip; and a second package including a logic chip configured to access the memory cell, wherein the capacitor structure is electrically connected to the memory chip and the logic chip.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.

Abstract: Provided are an apparatus and a method for removing noise for observation information of a weather radar, and more particularly, an apparatus and a method for removing noise for observation information of a weather radar capable of separating and removing second trip echoes corresponding to noise from precipitation echoes by simulating the reflectivity of the second trip echoes caused by a distance folding phenomenon shown in weather observation information generated using a weather radar. According to the present invention, in order to remove the second trip echo that occurs in the observation information measured in the volume observation radius during weather observation by setting the weather radar as the volume observation radius where the second trip echo occurs, the weather radar is set as a long-range observation radius in which a second trip echo exceeding the volume viewing radius does not occur.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: Provided is an apparatus for controlling a striking device. The apparatus for controlling the striking device equipped with a weapon to strike a target includes: a display unit which displays an image captured by a camera mounted on the striking device; a control unit which controls firing of the weapon; and a manipulation unit which transmits a fire signal to the control unit, wherein the control unit calculates the number of rounds of ammunition left in the striking device, calculates an accuracy rate which is a probability that the striking device will hit the target, and determines whether the target can be neutralized by considering the calculated number of rounds of ammunition left and the calculated accuracy rate for the target.

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: An operating device and method for remotely controlling an arming device. The method includes confirming a tracking image at each firing time point of a laser beam transmitted by the range finder; based on an image correlation value of a target locked on by a tracking gate in the tracking image exceeding a threshold value, determining that the target is normally locked on; determining whether the laser beam from the range finder hits the target determined as being normally locked on based on a center value of the tracking image and a center value of the tracking gate; and based on the laser beam from the range finder hitting the target normally locked on, determining a range measurement value measured by the range finder as a true value of the target and determining other range measurement values as wrong measurement values.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: The approach described herein uses the spatially and temporally controlled growth for programming 3D shapes and their motions, possibly with an unlimited number of degrees of freedom, could thus create dynamic 3D structures. The ability to program growth-induced 3D shapes and motions could transform the way engineering systems, such as robots, actuators, and artificial muscles, are designed. The concept is applicable to other programmable materials. The 2D printing approach for 3D material programming represents a scalable and customizable 3D manufacturing technology, which can potentially be integrated with biological systems and existing 2D fabrication methods and devices for broader applications.

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.