Patents by Inventor Kyung Wan Kim

Kyung Wan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170186485
    Abstract: An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 29, 2017
    Inventor: Kyung-Wan KIM
  • Publication number: 20170186813
    Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; an insulating layer interposed between the first and second electrode layers and containing a plurality of neutral defects; and an additional insulating layer interposed between the insulating layer and one or each of the first and second electrode layers, and being substantially free from neutral defects, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.
    Type: Application
    Filed: June 14, 2016
    Publication date: June 29, 2017
    Inventors: Kyung-Wan KIM, Jong-Chul LEE, Jong-Gi KIM
  • Publication number: 20170186948
    Abstract: A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.
    Type: Application
    Filed: May 24, 2016
    Publication date: June 29, 2017
    Inventor: Kyung-Wan KIM
  • Patent number: 9608165
    Abstract: A method of fabricating a light emitting diode (LED) includes: sequentially stacking a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a substrate; and separating the substrate into unit chips, and at the same time, forming a concavo-convex structure having the shape of irregular vertical lines in a side surface of the unit chip.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: March 28, 2017
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Kyung Wan Kim, Tae Kyoon Kim, Yeo Jin Yoon, Ye Seul Kim, Sang Hyun Oh, Jin Woong Lee, In Soo Kim
  • Publication number: 20170005138
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a line-type first electrode layer having at least one protrusion and extending in a first direction, and a plurality of memory elements, each memory element including a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively.
    Type: Application
    Filed: November 24, 2015
    Publication date: January 5, 2017
    Inventor: Kyung-Wan KIM
  • Publication number: 20170005137
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.
    Type: Application
    Filed: December 3, 2015
    Publication date: January 5, 2017
    Inventor: Kyung-Wan KIM
  • Publication number: 20160365384
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.
    Type: Application
    Filed: October 28, 2015
    Publication date: December 15, 2016
    Inventor: Kyung-Wan KIM
  • Publication number: 20160343839
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory includes first and second selecting elements coupled to a variable resistance element, and each of the first and second selecting elements includes a single-electron transistor.
    Type: Application
    Filed: October 9, 2015
    Publication date: November 24, 2016
    Inventor: Kyung-Wan KIM
  • Publication number: 20150311390
    Abstract: A method of fabricating a light emitting diode (LED) includes: sequentially stacking a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a substrate; and separating the substrate into unit chips, and at the same time, forming a concavo-convex structure having the shape of irregular vertical lines in a side surface of the unit chip.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: Kyung Wan KIM, Tae Kyoon KIM, Yeo Jin YOON, Ye Seul KIM, Sang Hyun OH, Jin Woong LEE, In Soo KIM
  • Publication number: 20150270441
    Abstract: Provided are a substrate having concave-convex patterns, a light-emitting diode (LED) including the substrate, and a method of fabricating the LED. The LED includes a substrate, and concave-convex patterns disposed in an upper surface of the substrate and having convexes and concaves defined by the convexes. Unit light-emitting device having a first conductive semiconduct or layer, an active layer, and a second conductive semiconductor layer disposed on the substrate in sequence is present.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Jae Kwon Kim, Sum Geun Lee, Kyung Wan Kim, Yeo Jin Yoon, Duk Il Suh, Ji Hye Kim
  • Patent number: 9112102
    Abstract: Provided are a light emitting diode (LED) and a method of fabricating the same. The LED includes a unit chip. The unit chip includes a substrate, and a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer which are sequentially stacked on the substrate. A concavo-convex structure having the shape of irregular vertical lines is disposed in a side surface of the unit chip.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 18, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Kyung Wan Kim, Tae Kyoon Kim, Yeo Jin Yoon, Ye Seul Kim, Sang Hyun Oh, Jin Woong Lee, In Soo Kim
  • Publication number: 20140231748
    Abstract: Provided are a substrate having concave-convex patterns, a light-emitting diode (LED) including the substrate, and a method of fabricating the LED. The LED includes a substrate, and concave-convex patterns disposed in an upper surface of the substrate and having convexes and concaves defined by the convexes. Unit light-emitting device having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer disposed on the substrate in sequence is present.
    Type: Application
    Filed: September 28, 2012
    Publication date: August 21, 2014
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Jae Kwon Kim, Sum Geun Lee, Kyung Wan Kim, Yeo Jin Yoon, Duk II Suh, Ji Hye Kim
  • Publication number: 20140117395
    Abstract: Provided are a light emitting diode (LED) and a method of fabricating the same. The LED includes a unit chip. The unit chip includes a substrate, and a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer which are sequentially stacked on the substrate. A concavo-convex structure having the shape of irregular vertical lines is disposed in a side surface of the unit chip.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Kyung Wan KIM, Tae Kyoon KIM, Yeo Jin YOON, Ye Seoul KIM, Sang Hyun OH, Jin Woong LEE, In Soo KIM
  • Patent number: 5940413
    Abstract: A method for detecting operational errors in a tester of a test system for determining whether a semiconductor device is good or failed includes a diagnostic test having the step of periodically inputting data to the device and checking whether the data can be retrieved intact from the tester. If not, then an operational error may be present in the tester. The method requires that the diagnostic test be carried out after a predetermined number of devices has been tested, and that the data inputted to the device during the diagnostic test be inputted to every I/O pin of the device. The diagnostic test includes inputting a value of 0 to each I/O pin, and then comparing the output of the device to a predetermined expected value. The diagnostic test also includes inputting a value of 1 to each I/O pin, and similarly comparing the output to an expected value.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: August 17, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Jin Kim, Joo Suk Kwak, Kyung Wan Kim, Jeong Ho Bang