Patents by Inventor Kyung Wook Paik

Kyung Wook Paik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030017327
    Abstract: Disclosed is a triple layered ACA film adapted for enhancing the adhesion strength of a typical single layer Anisotropic Conductive Film or for enhancing the adhesion strength of the ACA film in flip chip bonding. The triple layered ACA film of the invention comprises: a main ACA film based upon epoxy resin and containing conductive particles having a particle size of 3 to 10 &mgr;m and optionally non-conductive particles having a particle size of 0.1 to 1 &mgr;m; and adhesion reinforcing layers based upon epoxy resin and formed at both sides of the main ACA film.
    Type: Application
    Filed: July 12, 2002
    Publication date: January 23, 2003
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Wook Paik, Myung Jin Yim
  • Publication number: 20030008133
    Abstract: Disclosed are an anisotropic conductive film and a method of fabricating the same suitable for realizing an ultra-fine pitch COG (Chip On Glass) application. The anisotropic conductive film of the present invention is characterized in that 1-30% by volume nonconductive particles (polymer, ceramic, etc.) having a diameter {fraction (1/20)}-⅕ times as large as the conductive particles are added. According to the present invention, the anisotropic conductive film can prevent an electrical shorting between the bumps in bonding ultra fine pitch flip chip as well as in COG-bonding the driver IC. Accordingly, the anisotropic conductive film can be widely used in a communication field using ACA flip chip technology and universal flip chip packages.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 9, 2003
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Kyung wook Paik, Myung jin Yim
  • Publication number: 20020111423
    Abstract: Disclosed is a method for manufacturing a low dielectric constant conductive adhesive that is appropriate for a radio frequency packaging application. This method is characterized by mixing a thermosetting resin with surface-treated conductive particles and non-conductive particles for prevention of agglutination and thereby forming the conductive adhesive. The manufactured conductive adhesive is useful for a bonding material of the radio frequency packaging. According to the present invention, it is possible to obtain a flip chip bonding having superior mechanical and electrical performance compared with the conventional flip chip bonding art. Also, since the adhesive has a low high frequency loss and a low dielectric constant, it is possible to realize a flip chip package having a superior electrical performance. The conductive adhesive is particularly useful for the flip chip packaging of a device having a bandwidth of microwave and millimeter wave.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 15, 2002
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kyung wook Paik, Myung jin Yim, Woon seong Kwon
  • Patent number: 6362090
    Abstract: A method for forming flip chip bumps or UBM for a high speed copper interconnect chip, and more particularly to a method for forming a flip chip bump or UBM of copper/nickel, copper/nickel/copper or etc. which are carried out by a subsequent process of electroless copper plating and electroless nickel plating on a copper I/O pad. According to the method, both of electroless copper and nickel plating methods are used for forming electroless copper/nickel bumps of a copper interconnect chip so that advantages of the electroless copper plating, i.e. excellent selectivity and adhering strength to the copper chip pad and an advantage of the electroless nickel plating, i.e. excellent plating rate can be achieved at the same time.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: March 26, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Wook Paik, Jae Woong Nah, Young Doo Jeon, Myung Jin Yim
  • Patent number: 6238597
    Abstract: Disclosed is a method of preparing anisotropic conductive adhesives for flip chip interconnection on organic substrates, in which an epoxy resin as a binder is mixed with a conductive material and a non-conductive material at room temperature for 3 hours and then, with a coupling agent and a curing agent at room temperature for 1 hour. The anisotropic conductive adhesives are endowed with the electrical conductivity of conventional anisotropic conductive films and the mechanical reliability of an underfill used in a solder flip chip, simultaneously. The ACA shows fast hardenability and excellent coating and screening properties. The adhesive is spread over a plastic printed circuit board into which a flip chip is then brought. The flip chip and the plastic substrate can be bonded to each other using heat and pressure. Also, it is applicable for low-price flip chips and chip size packaging as well as for relevant-assembly packaging.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: May 29, 2001
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Myung Jin Yim, Kyung Wook Paik
  • Patent number: 6188129
    Abstract: The stackable semiconductor chip includes a semiconductor chip having pads on an upper surface thereof, and an adhesive formed on lateral surfaces of the semiconductor chip. A first insulation layer is formed over the upper surface of the semiconductor chip and the adhesive, and defines a plurality of through holes which expose the pads. Metal lines, formed on the first insulation layer, are connected to a respective one of the pads via a respective one of the through holes. A protective layer is formed on the metal lines and the first insulation layer. A plurality of stackable semiconductor chips are stacked by disposing double-sided adhesive between the stackable semiconductor chips. Then a plurality of external terminal pads are formed on one of the lateral surfaces of the stack of stackable semiconductor chips. Each external terminal pad is electrically connected to at least one of the metal lines in one of the stackable semiconductor chips.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: February 13, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kyung Wook Paik, Jin Su Kim, Hyoung Soo Ko
  • Patent number: 6124149
    Abstract: A stackable semiconductor chip package, methods of fabricating the chip package, and a stacked semiconductor chip module are disclosed. In the chip package or the chip module, lateral surfaces of each semiconductor chip are insulated with insulation regions that are formed while the chip is still part of an uncut wafer.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: September 26, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kyung Wook Paik, Jin Su Kim, Hyung Su Ko
  • Patent number: 5879964
    Abstract: A method for fabricating chip size packages which uses a lamination process, thereby not only achieving an improvement in the reliability of final electronic products, a reduction in the manufacturing costs, and a mass production resulting in a high marketability, but also being applicable to the fabrication of packages for both memory and non-memory chips and enabling the final electronic products to have high electronic performance while making the package size of the final electronic products not greater than 1.2 times the semiconductor chip size.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: March 9, 1999
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Wook Paik, Se Young Jang
  • Patent number: 5849623
    Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: December 15, 1998
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Kyung Wook Paik, Michael Gdula
  • Patent number: 5776275
    Abstract: A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: July 7, 1998
    Assignee: Martin Marietta Corporation
    Inventors: Vikram Bidare Krishnamurthy, Kyung Wook Paik, Mario Ghezzo, William Paul Kornrumpf, Eric Joseph Wildi
  • Patent number: 5675310
    Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: October 7, 1997
    Assignee: General Electric Company
    Inventors: Robert John Wojnarowski, James Wilson Rose, Kyung Wook Paik, Michael Gdula
  • Patent number: 5653841
    Abstract: A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: August 5, 1997
    Assignee: Martin Marietta Corporation
    Inventors: Vikram Bidare Krishnamurthy, Kyung Wook Paik, Mario Ghezzo, William Paul Kornrumpf, Eric Joseph Wildi