Patents by Inventor Kyungho Ryu
Kyungho Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137251Abstract: A receiver includes a first equalizer that receives an input data signal through a communication channel and equalizes the input data signal based on a first control code to generate a first equalization signal, a second equalizer that equalizes the first equalization signal based on a clock signal and a second control code to generate a second equalization signal, a clock data recovery circuit that restores the clock signal based on the second equalization signal, deserializes the second equalization signal, and outputs a deserialized second equalization signal, and a controller that adjusts the first control code and the second control code based on the deserialized second equalization signal.Type: ApplicationFiled: August 23, 2023Publication date: April 25, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungho RYU, Hyunwook LIM, Beomcheol KIM, Jung-Pil LIM
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Publication number: 20230421671Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventors: Yong-Yun PARK, Kyungho RYU, Kilhoon LEE, Hyunwook LIM, Youngmin CHOI, Kyungae KIM
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Publication number: 20230378963Abstract: The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.Type: ApplicationFiled: December 5, 2022Publication date: November 23, 2023Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Kyungho RYU, Yongil KWON, Kilhoon LEE, Jung-Pil LIM, Hyunwook LIM
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Patent number: 11758030Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.Type: GrantFiled: February 24, 2022Date of Patent: September 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Yun Park, Kyungho Ryu, Kilhoon Lee, Hyunwook Lim, Youngmin Choi, Kyungae Kim
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Publication number: 20230246801Abstract: A display device including: a timing controller outputting a reference dock signal and a data packet, wherein the data packet includes a dock signal embedded in a data signal; a dock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.Type: ApplicationFiled: March 30, 2023Publication date: August 3, 2023Inventors: Jungpil LIM, Kyungho RYU, Kilhoon LEE, Hyunwook LIM
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Publication number: 20230143912Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.Type: ApplicationFiled: November 11, 2022Publication date: May 11, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungho RYU, Kyongho KIM, Yongyun PARK, Kilhoon LEE, Yeongcheol RHEE, Taeho LEE, Hyunwook LIM
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Patent number: 11632228Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.Type: GrantFiled: September 16, 2021Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungpil Lim, Kyungho Ryu, Kilhoon Lee, Hyunwook Lim
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Publication number: 20220407949Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.Type: ApplicationFiled: February 24, 2022Publication date: December 22, 2022Inventors: Yong-Yun PARK, Kyungho RYU, Kilhoon LEE, Hyunwook LIM, Youngmin CHOI, Kyungae KIM
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Patent number: 11223468Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.Type: GrantFiled: March 8, 2021Date of Patent: January 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Kyungho Ryu, Kyongho Kim, Kilhoon Lee, Yeongcheol Rhee, Taeho Lee, Hyunwook Lim, Younghwan Chang, Sengsub Chun
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Publication number: 20220006604Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.Type: ApplicationFiled: September 16, 2021Publication date: January 6, 2022Inventors: Jungpil LIM, Kyungho RYU, Kilhoon LEE, Hyunwook LIM
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Patent number: 11133920Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.Type: GrantFiled: May 20, 2020Date of Patent: September 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungpil Lim, Kyungho Ryu, Kilhoon Lee, Hyunwook Lim
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Publication number: 20210067310Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.Type: ApplicationFiled: May 20, 2020Publication date: March 4, 2021Inventors: JUNGPIL LIM, Kyungho Ryu, Kilhoon Lee, Hyunwook Lim
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Patent number: 10763866Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.Type: GrantFiled: July 15, 2019Date of Patent: September 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungho Ryu, Hansu Pae, Kilhoon Lee, Jaeyoul Lee, Jung-Pil Lim, Hyunwook Lim
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Publication number: 20200169261Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.Type: ApplicationFiled: July 15, 2019Publication date: May 28, 2020Inventors: KYUNGHO RYU, HANSU PAE, KILHOON LEE, JAEYOUL LEE, JUNG-PIL LIM, HYUNWOOK LIM
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Publication number: 20180083641Abstract: A delay locked loop includes a first delay line and a second delay line. The first delay line is configured to generate a first delay clock, signal by passing an input clock, signal through a first number of logic gates among a plurality of logic gates and a second delay clock signal by passing the input clock signal through a second number of logic gates among the plurality of logic gates. The second delay line is configured to output an output clock signal based on one of a first signal having a first phase of the first delay clock signal, a second signal having a second phase of the second delay clock signal, and an interpolation signal having a third phase adjusted in stages by a reference value between the first phase and the second phase.Type: ApplicationFiled: July 14, 2017Publication date: March 22, 2018Inventors: Kyungho RYU, Dongmyung LEE, JaeYoul LEE, Kilhoon LEE, Jung-Pil LIM
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Patent number: 9574948Abstract: Provided is a temperature sensing circuit and a temperature sensing method including a delay unit delaying an input clock signal to generate a feedback clock signal, and including logic gates of which delay times are variable according to temperature, a delay control unit comparing the feedback clock signal with a reference clock signal and controlling each of the logic gates of the delay unit according to the comparison result, and an input signal control unit selecting, as the input clock signal, any one of the feedback clock signal and the reference clock signal to input the input clock signal to the delay unit.Type: GrantFiled: January 17, 2014Date of Patent: February 21, 2017Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Dong-Hun Jung, Young-Jae An
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Patent number: 9196337Abstract: A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.Type: GrantFiled: September 13, 2012Date of Patent: November 24, 2015Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Youngdon Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Patent number: 9035684Abstract: Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.Type: GrantFiled: January 17, 2014Date of Patent: May 19, 2015Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park
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Publication number: 20140204974Abstract: Provided is a temperature sensing circuit and a temperature sensing method including a delay unit delaying an input clock signal to generate a feedback clock signal, and including logic gates of which delay times are variable according to temperature, a delay control unit comparing the feedback clock signal with a reference clock signal and controlling each of the logic gates of the delay unit according to the comparison result, and an input signal control unit selecting, as the input clock signal, any one of the feedback clock signal and the reference clock signal to input the input clock signal to the delay unit.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Applicant: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook JUNG, Kyungho RYU, Dong-Hun JUNG, Young-Jae An
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Publication number: 20140203854Abstract: Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Inventors: Seong-Ook Jung, Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park