Patents by Inventor Kyungho Ryu
Kyungho Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8717811Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.Type: GrantFiled: March 5, 2013Date of Patent: May 6, 2014Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Patent number: 8693272Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.Type: GrantFiled: June 30, 2011Date of Patent: April 8, 2014Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Seung H. Kang
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Patent number: 8686772Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.Type: GrantFiled: September 13, 2012Date of Patent: April 1, 2014Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Jiwan Jung, Kyungho Ryu
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Patent number: 8670266Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.Type: GrantFiled: January 30, 2012Date of Patent: March 11, 2014Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Youngdon Jung, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Publication number: 20130286721Abstract: A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.Type: ApplicationFiled: September 13, 2012Publication date: October 31, 2013Applicants: Industry Academic Cooperation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Youngdon Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Patent number: 8531902Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.Type: GrantFiled: June 30, 2011Date of Patent: September 10, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung H. Kang
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Patent number: 8519758Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.Type: GrantFiled: March 11, 2011Date of Patent: August 27, 2013Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Won Lee, Donghwan Lee, Seong-Ook Jung, Heechai Kang, Kyungho Ryu, Donghoon Jung
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Publication number: 20130194862Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.Type: ApplicationFiled: January 30, 2012Publication date: August 1, 2013Applicant: QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Kyungho Ryu, Youngdon Jung, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Patent number: 8493116Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.Type: GrantFiled: September 14, 2011Date of Patent: July 23, 2013Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Jong-Ryun Choi, Seong-Ook Jung, Suho Kim, Heechai Kang, Kyungho Ryu
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Publication number: 20130120031Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.Type: ApplicationFiled: September 13, 2012Publication date: May 16, 2013Applicant: Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Seong-Ook JUNG, Jiwan JUNG, Kyungho RYU
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Patent number: 8432727Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.Type: GrantFiled: April 29, 2010Date of Patent: April 30, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, YonseiInventors: Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Seung H. Kang
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Patent number: 8406064Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.Type: GrantFiled: July 30, 2010Date of Patent: March 26, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Publication number: 20130003447Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung H. Kang
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Publication number: 20130002352Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Seung H. Kang
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Publication number: 20120062294Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.Type: ApplicationFiled: September 14, 2011Publication date: March 15, 2012Inventors: Jong-Ryun CHOI, Seong-Ook Jung, Suho Kim, Heechai Kang, Kyungho Ryu
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Publication number: 20120026783Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
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Publication number: 20110267874Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM INCORPORATEDInventors: Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Seung H. Kang
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Publication number: 20110221495Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Inventors: Won LEE, Donghwan Lee, Seong-Ook Jung, Heechai Kang, Kyungho Ryu, Donghoon Jung