Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.

Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.

Abstract: An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.

Abstract: The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).

Abstract: Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Abstract: An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor into the transistor array. Thus, the structure includes three basic components: a power inductor that spirals around the transistor array, the transistor array itself, and the transistor array metallization that is used to form a distributed inductance situated over the transistor array.

Abstract: A battery includes multiple conductive plates and a permeable electrolytic material and an ion membrane located between the conductive plates. The battery also includes at least one wire located within one or more of the permeable electrolytic material and the ion membrane. The at least one wire can be configured to regulate a flow of ions through the ion membrane based on an electrical signal flowing through the at least one wire. The at least one wire could also be configured to generate a magnetic field within the permeable electrolytic material based on another electrical signal flowing through the at least one wire. The battery could further include a temperature sensor wire within the permeable electrolytic material.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Abstract: In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.

Abstract: A battery includes multiple conductive battery plates and a complex electrolytic material located between the conductive battery plates. The battery also includes a conductive sensor wire located within the complex electrolytic material. The conductive sensor wire may be configured to generate a magnetic field within the complex electrolytic material based on an electrical signal flowing through the conductive sensor wire. The battery may further include a temperature sensor wire within the complex electrolytic material.

Abstract: In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.

Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

Abstract: A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer and are in electrical contact with a switching node of the power circuitry on each die respectively. The inductors are fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer for each die on the wafer. An insulating layer and then inductor coils are then formed over the plurality of magnetic core inductor members over each die. A layer of magnetic paste is also optionally provided over each inductor coil to further increase inductance.

Abstract: A magnetic guard ring is provided to reduce the susceptibility of a transformer-based data transmission to an externally generated magnetic field. The guard ring structure comprises strategically placed pieces of ferrite material, such as NiFe, that surround the transformer and “steer” the external magnetic field away from the transformer.

Abstract: An on-chip inductor structure includes a conductive inductor coil and a helical ferromagnetic inductor core that is formed to wrap around the conductive coil. The coil is space-apart from the ferromagnetic core by intervening dielectric material. The helical core structure includes at least one magnetic gap lithographically formed in the core.