Patents by Inventor Kyuwoon Hwang

Kyuwoon Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7531824
    Abstract: An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, William French
  • Patent number: 7525323
    Abstract: A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: April 28, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Kyuwoon Hwang, Peter I. Smeys, Andrei Papou
  • Patent number: 7507589
    Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
  • Patent number: 7463131
    Abstract: An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: December 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Kyuwoon Hwang, Peter J. Hopper, Robert Drury, Peter Johnson
  • Patent number: 7351593
    Abstract: A method is provided for forming the ferromagnetic core of an on-chip inductor structure. In accordance with the method, a static, permanent magnet is placed in proximity to a semiconductor wafer upon which the ferromagnetic core is being electroplated. The permanent magnet is place such that the magnetic field is orthogonal to the wafer. The “easy” axis material is that plated parallel parallel to the magnet's field and saturates at a lower applied field. The “hard” axis is that plated perpendicular to the applied magnetic filed and saturates later, at a higher current level. This plating approach results in optimum magnetic alignment of the ferromagnetic core so as to maximize both the field strength/magnetic flux slope and magnitude before magnetic material saturation occurs.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: April 1, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
  • Patent number: 7328609
    Abstract: A wireless tire pressure sensing system based upon a Schrader valve design is provided. The system includes a valve body, a valve pin and a compression element for sealing engaging the valve body and the valve pin to maintain tire pressure. A pressure sensing device mounted within the valve body and connected to valve pin senses the pressure within the tire and provides its signal to the valve pin. The valve pin is adapted as a component of an antenna that transmits a wireless pressure signal to a remote receiver/transmitter mounted on the vehicle. The receiver/transmitter transmits a corresponding signal to a vehicle control system that generates a warning signal when the tire pressure is below a threshold safety value.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: February 12, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Michael Mian, Kyuwoon Hwang, Robert Drury
  • Patent number: 7309639
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 18, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 7268410
    Abstract: Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Robert Drury
  • Patent number: 7250841
    Abstract: A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Philipp Lindorfer
  • Patent number: 7250842
    Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
  • Patent number: 7223680
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: May 29, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 7157891
    Abstract: An integrated DC—DC converter circuit in which multiple switched circuits operate in parallel to drive the output electrode with multiple pulsed charging voltages such that the corresponding respective output ripple voltage components combine with destructive interference, thereby reducing the net output ripple voltage.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: January 2, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Rob Drury, Peter J. Hopper, Kyuwoon Hwang, Peter Johnson
  • Patent number: 7098044
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: August 29, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6864581
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6853079
    Abstract: The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: February 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6740956
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 25, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6703710
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6660537
    Abstract: A conductive trace is formed over and insulated from a region of semiconductor material, such as a region adjacent to the n+ region of an n+/p− photodiode, and a sawtooth current is made to flow through the conductive trace. The sawtooth current induces charge carriers to move through the semiconductor material to a collection region in the semiconductor material.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Kyuwoon Hwang
  • Patent number: 6639784
    Abstract: A capacitor structure is formed in a wedge-shaped trench by forming alternating layers of insulating material and conductive material in the trench such that each layer of conductive material formed in the trench is electrically isolated from adjacent layers of conductive material formed in the trench. A first electrical contact is formed to electrically link in parallel a first set of alternating layers of conductive material. A second electrical contact is formed to electrically link in parallel a second set of alternating layers of conductive material. The two electrically isolated sets of inter-linked layers of conductive material define the interdigitated capacitor structure.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 28, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Peter Hopper, Philipp Lindorfer, Kyuwoon Hwang, Andy Strachan, Vladislav Vashchenko