Abstract: Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency.

Abstract: Aspects of a wireless apparatus for configuring a plurality of VCOs are provided. The apparatus may be a UE. The UE receives a configuration for a plurality of carriers. Each carrier corresponds to a different LO frequency. In addition, the UE determines a VCO frequency for generating each LO frequency. Further, the UE assigns each determined VCO frequency to each of a plurality of VCO modules based on a distance between the VCO modules and each of the determined VCO frequencies. The plurality of VCO modules are of a set of VCO modules including at least three VCO modules.

Abstract: A radio frequency (RF) front end having multiple low noise amplifiers modules is disclosed. In an exemplary embodiment, an apparatus includes at least one first stage amplifier configured to amplify received carrier signals to generate at least one first stage carrier group. Each first stage carrier group includes a respective portion of the carrier signals. The apparatus also includes second stage amplifiers configured to amplify the first stage carrier groups. Each second stage amplifier configured to amplify a respective first stage carrier group to generate two second stage output signals that may be output to different demodulation stages where each demodulation stage demodulates a selected carrier signal.

Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

Abstract: Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for dynamically adjusting a voltage-controlled oscillator (VCO) frequency, a local oscillator (LO) divider ratio, and/or a receive path when adding or discontinuing reception of a component carrier (CC) in a carrier aggregation (CA) scheme. This dynamic adjustment is utilized to avoid (or at least reduce) VCO, LO, and transmit signal coupling issues with multiple component carriers, with minimal (or at least reduced) current consumption by the VCO and the LO divider.

Abstract: A dual frequency synthesizer architecture for a wireless device operating in a time division duplex (TDD) mode is disclosed. In an exemplary design, the wireless device includes first and second frequency synthesizers. The first frequency synthesizer generates a first oscillator signal used to generate a first/receive local oscillator (LO) signal at an LO frequency for the receiver. The second frequency synthesizer generates a second oscillator signal used to generate a second/transmit LO signal at the same LO frequency for the transmitter. The two frequency synthesizers generate their oscillator signals to obtain receive and transmit LO signals at the same LO frequency when the wireless device operates in the TDD mode.

Abstract: Receiver circuits that can be reconfigured to generate test signals in a wireless device are disclosed. In an exemplary design, an apparatus includes a mixer and an amplifier. The mixer downconverts an input radio frequency (RF) signal based on a local oscillator (LO) signal in a first mode. The amplifier, which is formed by at least a portion of the mixer, amplifies the LO signal and provides an amplified LO signal in a second mode. In another exemplary design, an apparatus includes an amplifier and an attenuator. The amplifier receives and amplifies an input RF signal in a first mode. The attenuator, which is formed by at least a portion of the amplifier, receives and passes an LO signal in a second mode.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating a transceiver for wireless communications. One example method generally includes configuring a first oscillating signal as an input signal to at least a portion of a receiver (RX) path, calibrating a residual sideband (RSB) of the receiver path using a second oscillating signal as a local oscillating signal for the receiver path, and calibrating an RSB of a transmitter (TX) path by routing an output of the transmitter path to the receiver path, after calibrating the RSB of the receiver path. Another example method generally includes routing an output of a transmitter path to a receiver path, using a first local oscillating signal for the transmitter path, using a second local oscillating signal for the receiver path, and measuring an output of the receiver path as a local oscillator (LO) leakage for the transmitter path.

Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.

Abstract: Techniques for performing analog calibration of a receiver to optimize a second-order input intercept point (IIP2). In an aspect, a signal generator modeling an interferer is coupled to an adjustable input of a receiver, e.g., a gate bias voltage of a mixer. For example, the signal generator output may be a single-tone on-off keying (OOK) modulated signal. The mixer mixes the signal down to baseband, wherein an analog correlator correlates the down-converted signal with the known sequence of bits used to perform the OOK modulation. The analog correlation output is then provided to drive the bias voltage in the mixer, e.g., one or more gate voltages of transistors in the differential mixer, to optimize the overall receiver IIP2. Further aspects of the disclosure provide for calibrating receivers having multiple LNA's, and also dual or diversity receivers having multiple receive paths.

Abstract: Techniques for performing analog calibration of a receiver to optimize a second-order input intercept point (IIP2). In an aspect, a signal generator modeling an interferer is coupled to an adjustable input of a receiver, e.g., a gate bias voltage of a mixer. For example, the signal generator output may be a single-tone on-off keying (OOK) modulated signal. The mixer mixes the signal down to baseband, wherein an analog correlator correlates the down-converted signal with the known sequence of bits used to perform the OOK modulation. The analog correlation output is then provided to drive the bias voltage in the mixer, e.g., one or more gate voltages of transistors in the differential mixer, to optimize the overall receiver IIP2. Further aspects of the disclosure provide for calibrating receivers having multiple LNA's, and also dual or diversity receivers having multiple receive paths.

Abstract: A wireless device includes: an antenna; and a polar-modulation transmitter coupled to the antenna and configured for two-point modulation, the transmitter including: a data input; a first signal path including a multiplier coupled to the data input and a voltage-controlled oscillator gain adaptation module coupled to the multiplier and configured to provide a gain value to the multiplier; and a second signal path coupled to the data input and including an analog phase-locked loop (PLL) including a voltage-controlled oscillator (VCO) coupled to the first signal path.

Abstract: A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

Abstract: A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit digital values. Each multi-bit value is indicative of a time difference between an edge of FR and a corresponding edge of FV. The PDC decoder portion includes sequential logic elements that are clocked to capture the multi-bit digital values. In order to prevent metastability, the timing of when the sequential logic elements are clocked to capture the multi-bit digital values is adjusted as a function of the phase difference between FR and FV. In one specific example, if the phase difference is small then the falling edge of FR is used to clock the sequential logic elements, whereas if the phase difference is large then the rising edge of FR is used.

Abstract: A dual frequency synthesizer architecture for a wireless device operating in a time division duplex (TDD) mode is disclosed. In an exemplary design, the wireless device includes first and second frequency synthesizers. The first frequency synthesizer generates a first oscillator signal used to generate a first/receive local oscillator (LO) signal at an LO frequency for the receiver. The second frequency synthesizer generates a second oscillator signal used to generate a second/transmit LO signal at the same LO frequency for the transmitter. The two frequency synthesizers generate their oscillator signals to obtain receive and transmit LO signals at the same LO frequency when the wireless device operates in the TDD mode.

Abstract: A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

Abstract: A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit digital values. Each multi-bit value is indicative of a time difference between an edge of FR and a corresponding edge of FV. The PDC decoder portion includes sequential logic elements that are clocked to capture the multi-bit digital values. In order to prevent metastability, the timing of when the sequential logic elements are clocked to capture the multi-bit digital values is adjusted as a function of the phase difference between FR and FV. In one specific example, if the phase difference is small then the falling edge of FR is used to clock the sequential logic elements, whereas if the phase difference is large then the rising edge of FR is used.

Abstract: A novel form of an integrated variable inductor uses an on-chip transformer together with a variable capacitor. The variable capacitor can either be a varactor or a switched capacitor array and is connected to the secondary coil of the transformer. By changing the capacitance at the secondary coil of a transformer, the equivalent inductance looking into the primary coil of the transformer can be adjusted. With another capacitor in parallel to the primary coil, two different modes of resonance inherently exist, and a very wide frequency tuning range can be achieved by combining the two modes.

Abstract: A novel form of an integrated variable inductor uses an on-chip transformer together with a variable capacitor. The variable capacitor can either be a varactor or a switched capacitor array and is connected to the secondary coil of the transformer. By changing the capacitance at the secondary coil of a transformer, the equivalent inductance looking into the primary coil of the transformer can be adjusted. With another capacitor in parallel to the primary coil, two different modes of resonance inherently exist, and a very wide frequency tuning range can be achieved by combining the two modes.