Abstract: A bond pad connector to be disposed on a stretchable substrate and adapted to secure an electronic component thereon. The bond pad connector includes two spaced apart bond pads that are adapted to be disposed on the stretchable substrate to face each other. Each of the two bond pads is adapted to be connected to a respective conductive trace and includes: a stress relieve component that is adapted to be connected to the conductive trace, the stress relieve component being formed with a central hole; and an extension component extending from the stress relieve component and opposite to the conductive trace. The electronic component is secured onto the bond pad connector by attaching the electronic component to, for each of the bond pads, at least a part of the extension component.

Abstract: Systems, methods, and apparatuses are provided for diagnosing auto-immune diseases such as systemic lupus erythematosus (SLE) based on the sizes, methylation levels, and/or genomic characteristics of circulating DNA molecules. Patients provide blood or other tissue samples containing cell-free nucleic molecules for analysis. Massively parallel and/or methylation-aware sequencing can be used to determine the sizes and methylation levels of individual DNA molecules and identify the number of molecules originating from different genomic regions.

Abstract: A flexible composite substrate for a wearable antenna includes a fabric sheet and a single-layer dielectric film immersed into the fabric sheet. The single-layer dielectric film includes a dielectric resin matrix and a low dielectric loss material which is mixed with the dielectric resin matrix and which serves as a wireless functional dielectric interface material.

Abstract: A rework patch for an electronic circuit includes a flexible patch body and at least two patch traces. The electronic circuit includes a substrate, at least two board traces formed on the substrate, and at least one defect portion within at least one of the board traces. The patch body is attached to the substrate to partially cover each of the board traces and to cover the defect portion. The patch traces are formed on the patch body. A pattern of the patch traces corresponds to a pattern of a portion of the board traces covered by the patch body.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: Various embodiments are described herein for a testing system for performing burn-in testing of electronic devices under a test temperature range using at least one test chamber and a tester. The at least one test chamber is doorless and has a frame defining a chamber opening for receiving at least one burn-in board containing the electronic devices. The tester includes a main frame, a plurality of carrier magazines mounted to the main frame and containing the at least one burn-in board containing the electronic devices, a door panel at a front end of the tester to allow for access into the tester; and a wall panel disposed on a surface opposite the door panel. The wall panel is placed adjacent and secured to the chamber opening of the at least one test chamber to provide an air and temperature seal during testing.

Abstract: The technology described herein is directed to methods and compositions for the treatment of hypertension, e.g. pulmonary arterial hypertension, relating to inhibition of TGF?1, TGF?3, and/or GDF-15.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: The technology described herein is directed to methods and compositions for the treatment of hypertension, e.g. pulmonary arterial hypertension, relating to inhibition of TGF?1, TGF?3, and/or GDF-15.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: Various embodiments are described herein for a testing system for performing burn-in testing of electronic devices under a test temperature range using at least one test chamber and a tester. The at least one test chamber is doorless and has a frame defining a chamber opening for receiving at least one burn-in board containing the electronic devices. The tester includes a main frame, a plurality of carrier magazines mounted to the main frame and containing the at least one burn-in board containing the electronic devices, a door panel at a front end of the tester to allow for access into the tester; and a wall panel disposed on a surface opposite the door panel. The wall panel is placed adjacent and secured to the chamber opening of the at least one test chamber to provide an air and temperature seal during testing.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.