Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: The technology described herein is directed to methods and compositions for the treatment of hypertension, e.g. pulmonary arterial hypertension, relating to inhibition of TGF?1, TGF?3, and/or GDF-15.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: Pharmaceutical compositions comprising 3-aminoisoxazolopyridine compounds of the Formula I having IDO1 and/or TDO inhibitory activity are described, where W is CR1, N or N-oxide; X is CR2, N or N-oxide; Y is CR3, N or N-oxide; Z is CR4, N or N-oxide; and at least one of W, X, Y, and Z is N or N-oxide; and R9 and R10 are as defined. Also described are methods of using such compounds in the treatment of various conditions, such as cancer.

Abstract: The technology described herein is directed to methods and compositions for the treatment of hypertension, e.g. pulmonary arterial hypertension, relating to inhibition of TGF?1, TGF?3, and/or GDF-15.

Abstract: An automatic distress alarming method includes that: A. a distress alarm automatically sends out a sound and light alarming signal; B. the distress alarm automatically sends a distress signal and a GPS signal to a mobile phone; C. the distress alarm sends out the distress signal and the GPS signal by a manual operation; D. a disconnected distress alarm sends out the distress signal and the GPS signal. And its system includes a microprocessor U1, a driving chip U2, a wireless transmitting module U3, a switching circuit of an angular rate sensor, a GPS circuit, a storage device, a reset button, a manual operation alarming switch, a manual operation communicating switch and a disconnecting alarming button.

Abstract: An automatic distress alarming method includes that: A. a distress alarm automatically sends out a sound and light alarming signal; B. the distress alarm automatically sends a distress signal and a GPS signal to a mobile phone; C. the distress alarm sends out the distress signal and the GPS signal by a manual operation; D. a disconnected distress alarm sends out the distress signal and the GPS signal. And its system includes a microprocessor U1, a driving chip U2, a wireless transmitting module U3, a switching circuit of an angular rate sensor, a GPS circuit, a storage device, a reset button, a manual operation alarming switch, a manual operation communicating switch and a disconnecting alarming button.

Abstract: Various embodiments are described herein for testing memory devices more effectively and taking corrective action or for identifying memory devices. For example, a particular set of memory cells may be used for testing and/or for identifying a memory device. In other cases, memory testing may be done with a particular subset of test patterns.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Various embodiments are described herein for a system and a method for increasing reliability of a secondary storage device used with a computing system where the secondary storage device contains a memory buffer, a controller, and non-volatile memory. The method may comprise initializing a test of the memory buffer; testing at least one memory block of the memory buffer; discontinuing use of a given memory block of the memory buffer if a defective memory location is detected for the given memory block; and storing test results for the memory buffer.

Abstract: Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system.

Abstract: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, and the solid operating timing window used to determine a key timing index. A method for determining the solid operating timing window is disclosed. A plurality of sets of operating parameters is generated. For each of the plurality of sets of operating parameters, the respective set of operating parameters is applied to a test environment. The integrated circuit is then operated under the applied respective set of operating parameters. A determining a data valid window is determined for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of sets of operating parameters, where the solid operating timing window is defined as the logical intersection of the determined data valid windows such that the integrated circuit will return valid sample.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system.

Abstract: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index provides an indication of the quality of an integrated circuit over a range of operating conditions. In at least one embodiment a method is provided, the method comprising generating a plurality of combinations of operating parameters, for each of the plurality of combinations of operating parameters setting the respective combination of operating parameters, operating the integrated circuit under the set respective combination of operating parameters, and determining a data valid window for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of combinations of operating parameters, where the solid operating timing window is the logical intersection of the determined data valid windows.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.