Abstract: Embodiments described herein relate to an optical device and methods of forming an optical device. The optical device includes a substrate, an illumination source, a capping layer, an encapsulation layer, and a passivation layer. The encapsulation layer includes a first atomic layer deposition (ALD) layer, a chemical vapor deposition (CVD) layer, and a second ALD layer. The method includes disposing a capping layer over an illumination layer, the illumination layer disposed over a substrate in a processing chamber; disposing a first atomic layer deposition (ALD) layer over the capping layer; disposing a chemical vapor deposition (CVD) layer over the first ALD layer; disposing a second ALD layer over the CVD layer; and disposing a passivation layer over the second ALD layer.

Abstract: A method can include removing material from a first side of a diffuser block to form a back-side gradient surface of a diffuser, wherein the back-side gradient surface is a first concave surface, after removing the material from the first side, removing material from a second side of the diffuser block to form a front-side gradient surface of the diffuser, wherein the front-side gradient surface is a second concave surface, and forming a plurality of opening structures through the front-side gradient surface to the back-side gradient surface.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display, such as an organic light-emitting diode (OLED) display, are provided. In one example, a sub-pixel includes a substrate, adjacent overhang structures, an anode, an OLED material, a cathode, an encapsulation layer stack. The encapsulation layer stack includes a first layer, a second layer disposed over the first layer, and a third layer. The first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each overhang structure, and a third portion disposed under an underside surface of an extension of each overhang structure. A gap is defined by contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed over the second layer outside of the gap.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.

Abstract: An assembly includes a backing plate and a diffuser plate configured to be disposed under the backing plate. The diffuser plate forms purge holes in a first region of the diffuser plate between a diffuser plate upper surface and a diffuser plate lower surface. The diffuser plate forms perforated area holes in a second region of the diffuser plate between the diffuser plate upper surface and the diffuser plate lower surface. Each of the perforated area holes has a first width at the diffuser plate upper surface and a second width at the diffuser plate lower surface. The second width is larger than the first width.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: Embodiments of the disclosure relate to articles and transistor structures and methods of preparation and use thereof, including a substrate and an amorphous oxide film overlaying at least a portion of the substrate, where the amorphous oxide film includes a first oxide and a second oxide. The first oxide can include zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof, the second oxide can include silicon dioxide (SiO2), aluminum oxide (Al2O3), nitric oxide (NO) or combinations thereof. The amorphous oxide film can conformal and have a porosity of less than about 1% and may have a dielectric constant (k) of about 8 to about 28.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2eV?1 to about 5e11 cm?2eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: The present disclosure relates to a gas confiner assembly designed to reduce the non-uniform deposition rates by confining the gas flow and changing the local gas flow distribution near the edge regions of the substrate. The material, size, shape and other features of the gas confiner assembly can be varied based on the processing requirements and associated deposition rates. In one embodiment, a gas confiner assembly for a processing chamber comprises a gas confiner configured to decrease gas flow and compensate for high deposition rates on edge regions of substrates. The gas confiner assembly also comprises a cover disposed below the gas confiner. The cover is configured to prevent a substrate support from being exposed to plasma.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2eV?1 to about 5e11 cm?2eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.