Patents by Inventor Lai ZHAO
Lai ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130923Abstract: An adaptive seat massage system and a method of controlling the same include a massage module providing a massage function in a plurality of regions of a seat; a pressure measurement module detecting pressure applied to the seat by a user in the regions of the seat and transmits pressure measurement signal corresponding to respective regions among the plurality of regions; and a control module determining whether to operate the massage module in at least one region based on the pressure measurement signal received from the pressure measurement module, determining, when the massage module is operated in the at least one region, an operating mode of the massage module in the at least one region based on the pressure measurement signal, and transmitting a control signal corresponding to the determined operating mode to the massage module to control an operation of the massage module in the at least one region.Type: ApplicationFiled: December 12, 2022Publication date: April 25, 2024Applicants: Hyundai Motor Company, Kia CorporationInventors: Ming LI, Joo Hwan SON, Hai Yan ZHAO, Xiang Lai NIAN, Junshuai CAO, Shinjin KANG, Shi Hua WANG
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Publication number: 20240120349Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Xiangxin RUI, Lai ZHAO, Jrjyan Jerry CHEN, Soo Young CHOI, Yujia ZHAI
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Publication number: 20240088301Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2eV?1 to about 5e11 cm?2eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.Type: ApplicationFiled: April 27, 2023Publication date: March 14, 2024Inventors: Jianheng LI, Lai ZHAO, Yujia ZHAI, Soo Young CHOI
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Patent number: 11894396Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.Type: GrantFiled: January 7, 2022Date of Patent: February 6, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
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Patent number: 11895872Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.Type: GrantFiled: July 21, 2021Date of Patent: February 6, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Jung Bae Kim, Dong Kil Yim, Soo Young Choi, Lai Zhao
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HYBRID HIGH-K DIELECTRIC MATERIAL FILM STACKS COMPRISING ZIRCONIUM OXIDE UTILIZED IN DISPLAY DEVICES
Publication number: 20230369354Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.Type: ApplicationFiled: July 12, 2023Publication date: November 16, 2023Inventors: Xiangxin RUI, Lai ZHAO, Jrjyan Jerry CHEN, Soo Young CHOI, Yujia ZHAI -
Patent number: 11773489Abstract: The present disclosure relates to a gas confiner assembly designed to reduce the non-uniform deposition rates by confining the gas flow and changing the local gas flow distribution near the edge regions of the substrate. The material, size, shape and other features of the gas confiner assembly can be varied based on the processing requirements and associated deposition rates. In one embodiment, a gas confiner assembly for a processing chamber comprises a gas confiner configured to decrease gas flow and compensate for high deposition rates on edge regions of substrates. The gas confiner assembly also comprises a cover disposed below the gas confiner. The cover is configured to prevent a substrate support from being exposed to plasma.Type: GrantFiled: January 30, 2015Date of Patent: October 3, 2023Assignee: Applied Materials, Inc.Inventors: Lai Zhao, Qunhua Wang, Robin L. Tiner, Soo Young Choi, Beom Soo Park
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Hybrid high-k dielectric material film stacks comprising zirconium oxide utilized in display devices
Patent number: 11742362Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.Type: GrantFiled: September 28, 2021Date of Patent: August 29, 2023Assignee: APPLIED MATERIAL, INC.Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai -
Patent number: 11670722Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2eV?1 to about 5e11 cm?2eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.Type: GrantFiled: June 2, 2022Date of Patent: June 6, 2023Assignee: Applied Materials, Inc.Inventors: Jianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
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Publication number: 20230122134Abstract: A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.Type: ApplicationFiled: October 19, 2021Publication date: April 20, 2023Inventors: Changling Li, Lai Zhao, Gaku Furuta, Soo Young Choi, Robin L. Tiner, David Atchley, Ganesh Babu Chandrasekaran
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Patent number: 11600642Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.Type: GrantFiled: May 27, 2021Date of Patent: March 7, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Xiangxin Rui, Soo Young Choi, Shinichi Kurita, Yujia Zhai, Lai Zhao
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Publication number: 20220293793Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2eV?1 to about 5e11 cm?2eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Inventors: Jianheng LI, Lai ZHAO, Yujia ZHAI, Soo Young CHOI
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Patent number: 11380801Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.Type: GrantFiled: August 28, 2020Date of Patent: July 5, 2022Assignee: Applied Materials, Inc.Inventors: Jianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
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Publication number: 20220130873Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: Xiangxin RUI, Lai ZHAO, Jrjyan Jerry CHEN, Soo Young CHOI, Yujia ZHAI
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Patent number: 11239258Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.Type: GrantFiled: July 11, 2017Date of Patent: February 1, 2022Assignee: Applied Materials, Inc.Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
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HYBRID HIGH-K DIELECTRIC MATERIAL FILM STACKS COMPRISING ZIRCONIUM OXIDE UTILIZED IN DISPLAY DEVICES
Publication number: 20220013547Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Inventors: Xiangxin RUI, Lai ZHAO, Jrjyan Jerry CHEN, Soo Young CHOI, Yujia ZHAI -
Publication number: 20210376032Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.Type: ApplicationFiled: July 21, 2021Publication date: December 2, 2021Inventors: Jung Bae KIM, Dong Kil YIM, Soo Young CHOI, Lai ZHAO
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Hybrid high-k dielectric material film stacks comprising zirconium oxide utilized in display devices
Patent number: 11145683Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.Type: GrantFiled: July 12, 2017Date of Patent: October 12, 2021Assignee: Applied Materials, Inc.Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai -
Patent number: 11123837Abstract: Methods for manufacturing a diffuser plate for a PECVD chamber are provided. The methods provide for applying a compliant abrasive medium to round the sharp edges at corners of the output holes on a contoured downstream side of a gas diffuser plate. By rounding the edges of the output holes reduces the flaking of deposited materials on the downstream side of the gas diffuser plate and reduces the amount of undesirable particles generated during the PECVD deposition process.Type: GrantFiled: December 22, 2017Date of Patent: September 21, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Ilyoung Hong, Lai Zhao, Jianhua Zhou, Robin L. Tiner, Gaku Furuta, Shinichi Kurita, Soo Young Choi
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Publication number: 20210288084Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Inventors: Xiangxin RUI, Soo Young CHOI, Shinichi KURITA, Yujia ZHAI, Lai ZHAO