Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes including a mode that encodes data in a clock signal. A method includes providing a clock signal that controls timing of transactions conducted over a serial bus, transmitting a first pair of data bytes at double data rate over a first wire of the serial bus in a first transaction, modulating the clock signal during the first transaction to provide a modulated clock signal that encodes at least one additional data byte, and transmitting the modulated clock signal over a second wire of the serial bus during the first transaction.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Systems, methods, and apparatus for one wire communication are disclosed. A method performed at a master device includes driving a wire coupling the master device to a slave device from a first voltage to a second voltage, causing a line driver in the master device to present a high impedance to the wire after the wire has been driven to the second voltage, determining that the slave device is communicating a first bit-value when the wire has been driven to the first voltage before a threshold time period has elapsed, determining that the slave device is communicating a second bit-value when the wire is at the second voltage after the threshold time period has elapsed, and driving the wire to transition from the second voltage to the first voltage when the wire is at the second voltage after the threshold time period has elapsed.

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for optimizing bus latency associated with a serial bus using staggered bidirectional transmission within a transaction or datagram are described. A method performed at a device coupled to a serial bus includes initiating a transaction between the first device and a second device to exchange a datagram with the second device in a first direction over the serial bus, and exchanging one or more bytes of data with the second device in a second direction over the serial bus before the datagram has been completely transmitted. The first device and the second device alternate as transmitters on the serial bus such that direction of data transmission is staggered on the serial bus. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

Abstract: Increased data rates over a serial bus are enabled without increasing clock frequency. A method performed at a device coupled to a serial datalink includes transmitting a one-bit sequence start condition over a data wire of a datalink, providing a command field in the pulse-width modulated datagram, where a first-transmitted bit of the command field identifies the datagram as a write command directed to a register located at address zero, and providing data in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value. The sequence start condition has a first edge that commences transmission of a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram.

Abstract: Systems, methods, and apparatus for increasing register space on a slave device are described. A method performed at a device coupled to a serial bus includes receiving a datagram from a serial bus, the datagram including a command directed to a first register address in a first page of registers, writing data in a payload of the datagram to a second register address in a second page of registers when the command is a write command, and reading data from the second register address in the second page of registers when the command is a read command. The second register address is identified in the datagram when the command is a write command.

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

Abstract: Systems, methods, and apparatus for improving bus latency are described. Clock-cycle overhead associated with the transmission of trigger activation information may be reduced through the use of optimized datagram structures for register-configurable trigger activation mechanisms. A first mechanism defines a command code with a first Trigger-Activation datagram, and a second mechanism defines a command code with a second Trigger-Activation datagram that uses a 4-bit Magic-ID and eliminates 18 clock cycles from the conventional Extended Register Write datagram structure. A method performed at a device coupled to a serial bus includes generating a datagram that does not have an address field, populating a data payload of the datagram with trigger activation information directed to a plurality of slave devices coupled to a serial bus, and transmitting the datagram over the serial bus. Transmission of the datagram serves as a trigger that causes a configuration change in at least one slave device.

Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

Abstract: Systems, methods, and apparatus for improving latency of a serial bus are described. A method performed at a device coupled to a serial bus includes writing a first data byte received in a first field of a datagram from a serial bus to a first register in the slave device, modifying the address pointer by adding or subtracting a stride value provided in a second field of the datagram to obtain a modified address pointer, and writing a second data byte received in a third field of the datagram to a second register in the slave device. The first register may be located at an address indicated by an address pointer and the second register may be located at an address indicated by the modified address pointer. The first register and the second register may be located at non-contiguous addresses.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.