Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

Abstract: Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits.

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

Abstract: Systems, apparatus, methods and techniques that can provide optimized low-latency communications between different devices such that GPIO signals may be carried as virtual signals. A virtual GPIO finite state machine in a first device is provided that can consolidate GPIO-related events by initiating a wait period after a first-occurring event and that has a duration selected to permit one or more later-occurring events to be detected before transmission of virtual GPIO data over a data communication bus to a second device. One method may include initiating a wait period after detecting a first change in GPIO state, refraining from transmitting virtual GPIO data during the wait period, detecting occurrence of a second change in GPIO state during the wait period, and transmitting virtual GPIO data corresponding to the first and second changes in GPIO state over the serial bus after the wait period has expired.

Abstract: Systems, methods, and apparatus for sharing a serial bus interface among devices having different operating speeds are described. A sequence of commands on a data line of the serial bus are generated including a start condition signal and a device identifier signal where the identifier signal is part of a command frame in the sequence of commands. The sequence of commands is transmitted on the data line concurrent with the transmission of a clock signal on a clock line of the serial bus during the duration of the device identifier signal. The frequency of the clock signal is set at a first clock frequency for the duration of the device identifier signal where the first clock frequency is a frequency supported among all devices coupled to the serial bus, allowing all devices to decode an initial sequence, whether the devices are configured for higher frequency operation or not.

Abstract: A device for activating trigger data has a serial bus interface and a processing circuit coupled to the serial bus interface. The processing circuit is configured to receive a plurality of trigger data via a serial bus, receive a plurality of activation data via the serial bus, detect an activation scheme for activating a respective trigger data of the plurality of trigger data based on activation data corresponding to the respective trigger data, and activate the respective trigger data according to the detected activation scheme. If activated, each one of the plurality of trigger data respectively enables a corresponding operation to be performed at the device. Each one of the plurality of activation data respectively correspond to each one of the plurality of trigger data.

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a transmitting device includes receiving a datagram to be transmitted from the transmitting device to a receiving device, determining whether a first serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, determining whether a second serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, transmitting the datagram over the first serial bus when the first serial bus is available, and transmitting the datagram over the second serial bus when the second serial bus is available and when the first serial bus is unavailable. The datagram is associated with a latency budget. The first or second serial bus may be available to transmit the datagram when active and likely to transmit the datagram within a time limit defined by the latency budget.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Abstract: Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

Abstract: Systems, methods, and apparatus for optimizing bus turnaround in a master-driven serial bus are described. A method performed at a master device coupled to a serial bus includes configuring slave devices coupled to the serial bus with respective delay values that define bus turnaround wait periods, transmitting a first read command directed to a first slave device, receiving data after a first wait period initiated after the first read command has been sent, the first wait period being defined by a delay value configured in the first slave device, transmitting a second read command directed to a second slave device, and receiving data after a second wait period initiated after the second read command has been sent, the second wait period being defined by a delay value configured in the second slave device. The first wait period and the second wait period may have different durations.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.

Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.