Abstract: The present invention relates to bispecific anti-CCL2 antibodies binding to two different epitopes on human CCL2, pharmaceutical compositions thereof, their manufacture, and use as medicaments for the treatment of cancers, inflammatory, autoimmune and ophthalmologic diseases.

Abstract: The present invention relates to bispecific anti-CCL2 antibodies binding to two different epitopes on human CCL2, pharmaceutical compositions thereof, their manufacture, and use as medicaments for the treatment of cancers, inflammatory, autoimmune and ophthalmologic diseases.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: The present disclosure provides compositions and methods for using recombinant C1 metabolizing microorganisms capable of metabolizing sulfur containing compounds and other contaminants to biologically convert sour or acidic natural gas into high-value molecules, and to allow recovery of stranded oil.

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Abstract: The present disclosure provides compositions and methods for using recombinant C1 metabolizing microorganisms capable of metabolizing sulfur containing compounds and other contaminants to biologically convert sour or acidic natural gas into high-value molecules, and to allow recovery of stranded oil.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

Abstract: A temperature control apparatus for controlling operation of at least one temperature-modifying device includes a housing, a wireless communication module configured to communicate with a remote Internet-based server, and a controller in communication with the wireless communication module. The controller is configured to: (i) control operation of the temperature modifying device in response to a comparison of a measured ambient temperature with a setpoint temperature, (ii) in a user-selectable first mode of operation, during a first time period during a day, poll the remote server at a first rate of at least six times per hour, using the wireless communication module, for an instruction to change the setpoint temperature, and (iii) in the first mode of operation, during a second time period, poll the remote server at a second rate that is lower than the first rate, using the wireless communication module, for an instruction to change the setpoint temperature.

Abstract: A temperature control apparatus for controlling operation of at least one temperature-modifying device includes a housing, a wireless communication module configured to communicate with a remote Internet-based server, and a controller in communication with the wireless communication module. The controller is configured to: (i) control operation of the temperature modifying device in response to a comparison of a measured ambient temperature with a setpoint temperature, (ii) in a user-selectable first mode of operation, during a first time period during a day, poll the remote server at a first rate of at least six times per hour, using the wireless communication module, for an instruction to change the setpoint temperature, and (iii) in the first mode of operation, during a second time period, poll the remote server at a second rate that is lower than the first rate, using the wireless communication module, for an instruction to change the setpoint temperature.

Abstract: Hardware acceleration for batched sparse (BATS) codes is enabled. Hardware implementation of some timing-critical procedures can effectively offload computationally intensive overheads, for example, finite field arithmetic, Gaussian elimination, and belief propagation (BP) calculations, and this can be done without direct mapping of software codes to a hardware implementation. Suitable acceleration hardware may include pipelined multipliers configured to multiply input data with coefficients of a matrix associated with a random linear network code in a pipelined manner, addition components configured to add multiplier output to feedback data, and switches to direct data flows to and from memory components such that valid result data is not overwritten and such that feedback data corresponds to most recent valid result data. Acceleration hardware components (e.g., number and configuration) may be dynamically adjusted to modify BATS code parameters and adapt to changing network conditions.

Abstract: The present disclosure provides compositions and methods for using recombinant C1 metabolizing microorganisms capable of metabolizing sulfur containing compounds and other contaminants to biologically convert sour or acidic natural gas into high-value molecules, and to allow recovery of stranded oil.

Abstract: This invention relates to a class of ruthenium(II) bis(aryleneethynylene) complexes for use in bulk heterojunction (BHJ) solar cell devices, and the method of synthesizing thereof. This invention also relates to a BHJ solar cell device comprising the ruthenium(II) bis(aryleneethynylene) complex.