Patents by Inventor Lamine Benaissa

Lamine Benaissa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220349221
    Abstract: A device and a method for locking and/or unlocking a motor vehicle opening panel and vehicle having the device. The device includes a detection wall having an inner side and an opposite outer side, the outer side forming a contact detection region, and a detection component arranged against the inner side for detecting contact between a user's finger or hand and the outer side. The detection component includes a sensor having a layer of a piezoelectric material which has surface undulations in the form of ridges. The layer of piezoelectric material is configured to detect predetermined contact on the outer side with a view to controlling the locking or unlocking of the opening panel.
    Type: Application
    Filed: June 22, 2020
    Publication date: November 3, 2022
    Inventors: Frédérick REICHHELD, François BOLLIER, Christophe CAZES, Lamine BENAISSA, Jean-Sébastien MOULET
  • Publication number: 20220336266
    Abstract: A composite structure, intended for a planar co-integration of electronic components of different functions, the composite structure including from its base towards its surface: a support substrate made of a first material, the support substrate including cavities each opening into an upper face of the support substrate, the cavities being filled with at least one composite material consisting of a matrix of a crosslinked preceramic polymer, the matrix being charged with inorganic particles; and a thin film made of a second material, the thin film being bonded to the upper face of the support substrate and to the composite material.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 20, 2022
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Marilyne ROUMANIE, Christelle NAVONE, Lamine BENAISSA
  • Publication number: 20220298007
    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.
    Type: Application
    Filed: August 18, 2020
    Publication date: September 22, 2022
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry SALVETAT, Bruno GHYSELEN, Lamine BENAISSA, Caroline COUTIER, Gweltaz GAUDIN
  • Patent number: 11442571
    Abstract: A touch surface device, comprising at least: an element comprising a first face forming the touch surface and a second face opposite to the first face; an acoustic wave sensor including at least one portion of piezoelectric material disposed between two electrodes, the portion of piezoelectric material and both electrodes being structured by forming surface wavinesses as wrinkles, the sensor being secured to the second face of the element such that apexes or valleys of the wrinkles are in contact with the second face of the element; an electronic circuit coupled to the electrodes of the sensor and configured to identify, from an electric signal intended to be outputted from the electrodes of the sensor, at least one touch gesture made on the touch surface.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 13, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamine Benaissa, Jean-Sebastien Moulet
  • Patent number: 11401162
    Abstract: A process for transferring a useful layer to a carrier substrate including a first surface is provided, the process including the steps of: providing a donor substrate including a first surface, a weakened zone including implanted species, the useful layer, which is bounded by the weakened zone and by the first surface of the donor substrate, and an amorphous zone disposed, in the useful layer, parallel to the weakened zone; assembling, on a side of the first surface of the donor substrate and on a side of the first surface of the carrier substrate, the donor substrate with the carrier substrate by bonding, such that the amorphous zone is at least partially facing at least one cavity that is partially bounded by the first surface of the donor substrate; and splitting the donor substrate along the weakened zone so as to reveal the useful layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 2, 2022
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Lamine Benaissa, Thierry Salvetat
  • Patent number: 11380577
    Abstract: A method for transferring, from a donor substrate to a carrier substrate, a thin layer having a first coefficient of thermal expansion. This method comprises: —forming an embrittlement plane in the donor substrate; —forming an electrically insulating layer on the surface of the donor substrate and/or of the carrier substrate; —producing an assembly by placing the donor substrate and the carrier substrate in contact with one another via the insulating layer; —separating the assembly by fracturing along the embrittlement plane.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 5, 2022
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Lamine Benaissa, Marilyne Roumaine
  • Patent number: 11329188
    Abstract: A method of manufacturing electronic devices, including the successive steps of: a) growing, on a surface of a first substrate, a stack including at least one semiconductor layer; b) bonding a second substrate on a surface of the stack opposite to the first substrate, and then removing the first substrate; c) bonding a third substrate to a surface of the stack opposite to the second substrate, and then removing the second substrate; d) cutting the assembly including the third substrate and the stack into a plurality of first chips each including a portion of the stack; and e) bonding each first chip, by its surface opposite to the third substrate, to a surface of a fourth semiconductor substrate inside and on top of which a plurality of integrated control circuits have been previously formed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: May 10, 2022
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Lamine Benaissa, Marc Rabarot
  • Patent number: 11171158
    Abstract: A semiconductor on insulator type substrate, comprising at least: a support layer; a semiconductor surface layer; a buried dielectric layer located between the support layer and the semiconductor surface layer; a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material; in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 9, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann Lamy, Lamine Benaissa, Etienne Navarro
  • Patent number: 11127710
    Abstract: A transfer method includes steps of a) supplying a support layer having a first face, structures being assembled by their front face on the first face, and c) transferring the structures onto a host face of a host substrate. The support layer includes folding regions, between the structures, adapted to pass from a folded state to an unfolded state under the action of an external excitation. Between steps a) and c), a step b) is included of executing the external action in such a way as to make the folding regions pass from the folded state to the unfolded state such that the spacing between the structures varies.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 21, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamine Benaissa, Ismail Degirmencioglu
  • Patent number: 11024544
    Abstract: Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 1, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Lamine Benaissa, Laurent Brunet
  • Publication number: 20210125857
    Abstract: A method for transferring, from a donor substrate to a carrier substrate, a thin layer having a first coefficient of thermal expansion. This method comprises: —forming an embrittlement plane in the donor substrate; —forming an electrically insulating layer on the surface of the donor substrate and/or of the carrier substrate; —producing an assembly by placing the donor substrate and the carrier substrate in contact with one another via the insulating layer; —separating the assembly by fracturing along the embrittlement plane.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Inventors: Lamine Benaissa, Marilyne Roumaine
  • Publication number: 20210091742
    Abstract: A method for producing an adjustable bulk acoustic wave resonator comprising a transducer stack (E1) and a tuning stack (E2). According to the invention, transducer stack (E1) includes two defined electrodes (4, 6) and piezoelectric material (2), and stack (E2) includes a layer of piezoelectric material (8) and two defined electrodes (10, 12). The method includes: a) production of the transducer stack; b) formation of an electrically insulating layer on an electrode (6) of the transducer stack; c) formation of a defined electrode (10) of the tuning stack on the electrically insulting layer such that it is aligned with the electrodes of the transducer stack; d) assembly, on the electrode (10), of a substrate of piezoelectric material; e) fracturing of the substrate of piezoelectric material; and f) formation of the other defined electrode (12) of the tuning stack, aligned with the defined electrode (10).
    Type: Application
    Filed: December 21, 2018
    Publication date: March 25, 2021
    Inventors: Marie Gorisse, Alexandre Reinhardt, Lamine Benaissa, Jean-Sébastien Moulet
  • Publication number: 20210050476
    Abstract: A method of manufacturing electronic devices, including the successive steps of: a) growing, on a surface of a first substrate, a stack including at least one semiconductor layer; b) bonding a second substrate on a surface of the stack opposite to the first substrate, and then removing the first substrate; c) bonding a third substrate to a surface of the stack opposite to the second substrate, and then removing the second substrate; d) cutting the assembly including the third substrate and the stack into a plurality of first chips each including a portion of the stack; and e) bonding each first chip, by its surface opposite to the third substrate, to a surface of a fourth semiconductor substrate inside and on top of which a plurality of integrated control circuits have been previously formed.
    Type: Application
    Filed: August 12, 2020
    Publication date: February 18, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Lamine Benaissa, Marc Rabarot
  • Patent number: 10886158
    Abstract: The invention relates to a method for transferring structures on a host substrate, the method comprising the following steps in sequence: a) supply a temporary substrate comprising two main faces, the temporary substrate being stretchable, the structures being assembled with their front face on the first face; b) stretch the temporary substrate along at least one direction so as to increase the space between the structures along at least one direction, c) a step for transferring the plurality of structures on a host face of a host substrate, The temporary substrate comprises a matrix made of a stretchable material, and a plurality of inserts on which the structures are assembled, the inserts comprising a material with a Young's Modulus higher than that of the stretchable material.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 5, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Lamine Benaissa
  • Publication number: 20200401262
    Abstract: A touch surface device, comprising at least: an element comprising a first face forming the touch surface and a second face opposite to the first face; an acoustic wave sensor including at least one portion of piezoelectric material disposed between two electrodes, the portion of piezoelectric material and both electrodes being structured by forming surface wavinesses as wrinkles, the sensor being secured to the second face of the element such that apexes or valleys of the wrinkles are in contact with the second face of the element; an electronic circuit coupled to the electrodes of the sensor and configured to identify, from an electric signal intended to be outputted from the electrodes of the sensor, at least one touch gesture made on the touch surface.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 24, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamine BENAISSA, Jean-Sebastien MOULET
  • Patent number: 10734439
    Abstract: A method of manufacturing an optoelectronic device, including the successive steps of: a) transferring, onto a surface of a control integrated circuit including a plurality of metal connection pads, an active diode stack including at least first and second doped semiconductor layers of opposite conductivity types, so that the second layer of the stack is electrically connected to the metal pads of the control circuit; and b) forming in the active stack trenches delimiting a plurality of diodes connected to different metal pads of the control circuit.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 4, 2020
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Thales
    Inventors: François Templier, Lamine Benaissa, Marc Rabarot
  • Patent number: 10710192
    Abstract: A method includes steps a) providing the first structure successively including a first substrate, a first layer made from a metal base and a first metal-based metal oxide, b) providing the second structure successively including a second substrate, a second layer made from a second material and a second metal-based metal oxide, the first and second metal oxides presenting a standard free enthalpy of formation ?G°, the second material being chosen so that it has an oxide presenting a standard free enthalpy of formation strictly less than ?G°, c) bonding the first structure and second structure by direct adhesion, d) activating diffusion of the oxygen atoms of the first and second metal oxides to the second layer so as to form the oxide of the second material.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 14, 2020
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruno Imbert, Lamine Benaissa, Paul Gondcharton
  • Patent number: 10679963
    Abstract: A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: June 9, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruno Imbert, Lamine Benaissa, Paul Gondcharton
  • Publication number: 20200161336
    Abstract: A semiconductor on insulator type substrate, comprising at least: a support layer; a semiconductor surface layer; a buried dielectric layer located between the support layer and the semiconductor surface layer; a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material; in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 21, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann LAMY, Lamine BENAISSA, Etienne NAVARRO
  • Patent number: 10586810
    Abstract: A semiconductor on insulator type substrate, comprising at least: a support layer; a semiconductor surface layer; a buried dielectric layer located between the support layer and the semiconductor surface layer; a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material; in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 10, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann Lamy, Lamine Benaissa, Etienne Navarro