Abstract: A transformer includes a bobbin, a primary coil, a secondary coil, and a core assembly. The bobbin has a winding portion. At least one first winding groove and at least one second winding groove are formed on the winding portion. The first winding groove and the second winding groove are separated by a barrier. A notch is formed on the fringe portion of the barrier. The primary coil is wrapped in the first winding groove, and the secondary coil is wrapped in the second winding groove. The notched barrier increases the creepage distance between the primary coil and the secondary coil in meeting the safety standards.

Abstract: A transformer includes a winding frame, a primary coil, an insulating cover, a secondary coil, and a core assembly. The winding frame has a winding portion formed with a first side portion and a second side portion oppositely. A plurality of first pins and second pins are disposed on the first and second side portions, respectively. The primary coil is wrapped around the winding portion of the winding frame and connected to the first pins. The insulating cover is fitted over the primary coil. The secondary coil is wrapped around the insulating cover and connected to the second pins. The core assembly is arranged on the winding frame. A transformer assembling method is also disclosed. The coil wrapping process for the transformer can be expedited and associated cost can be reduced.

Abstract: According to the present invention, there is provided a method of providing a WORM storage system, the method including a sector-append capability. The method includes receiving data to be written to a WORM storage system. In addition, the method includes identifying a target sector at which the data is to be written. Also, the method includes determining if the received data can be added to the target sector. Moreover, the method includes adding the received data to the target sector if it is determined that the received data can be added to the target sector.

Abstract: An apparatus and computer program product determine a target data type in an environment having a plurality of levels. The plurality of levels comprise a source level, zero or more intermediate levels, and a target level. The zero or more intermediate levels are between the source level and the target level. A target data type representing a transformation of a data type of an associated datum as the datum passes from the source level through the zero or more intermediate levels to the target level is generated. The target data type comprises a sequence of nested transformation functions having an innermost transformation function and an outermost transformation function.

Abstract: A method and apparatus for displaying aircraft information. A selection of a piece of dynamic information is detected about an aircraft on a first display on a user interface. The piece of dynamic information is used to operate the aircraft and changes during operation of the aircraft. The piece of dynamic information selected from the first display is added to a custom display on the user interface. The custom display is displayed on the user interface on a display system for the aircraft.

Abstract: A method is disclosed for scheduling data management jobs on a computer system that uses a dual level scheduling method. Macro level scheduling using a chained timer schedules the data management job for execution in the future. Micro level scheduling using an algorithm controls the actual dispatch of the component requests of a data management job to minimize impact on foreground programs.

Abstract: A virtual binding system ensures that the WORM logic for protecting data immutability cannot be circumvented, effectively guaranteeing WORM property of a WORM storage system composed of rewritable magnetic hard disks. To close the security hole between the rewritable media and the WORM logic, virtual binding securely authenticates the legitimacy of a WORM logic controller before granting data access on a WORM storage media. Furthermore, the system verifies the legitimacy of the WORM logic controller during data access. This approach virtually binds together the WORM logic controller and the WORM storage media even though the WORM logic controller and the WORM storage media may be physically separate.

Abstract: Primary and secondary virtual machines each executing on a separate physical host and forming a fault-tolerant pair synchronize their execution with each other as closely as possible such that the secondary can take over execution of the primary with little or no disruption of service and no loss of data. To provide fast takeover, the execution latency between the two virtual machines is kept to a minimum by incrementally adjusting the CPU allocation to the primary virtual machine. The CPU allocation to the primary virtual machine decreases when the execution latency is large and increases when the execution latency is small. In order to maximize the performance of the primary virtual machine, the system seeks to maximize the CPU resource limit for the primary virtual machine for as long as possible while minimizing the execution latency.

Abstract: Provided is the composition of a peptide and its mutagenic version, or other derivatives with the same 3-D structure with activity to bind the extracellular domain of PDGFR-?, or -?, but does not dimerize by itself, wherein said peptide comprises the sequence shown as SEQ ID NO: 1, 2 or 3. Also provided is the composition of the nucleotide sequence encoding said peptide and its derivatives, and the usage of said peptide and derivatives of the peptide in preparation of medicine for the prevention and treatment of fibrosis diseases, such as liver, kidney, and lung fibrosis, primary cancer, and cancer metastasis, especially stomach cancer, liver cancer, breast cancer, and lung cancer.

Abstract: A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.

Abstract: The invention relates to a system and method for providing efficient policy rule updates in policy-based data management. More particularly, the invention relates to a system and method for restraining the size of the set of data objects to be examined after a policy rule evaluation.

Abstract: An inexact query transformation system selects a query element from a query statement. If an inexact transformation improves the query performance, the system prioritizes the candidate transformation rules applicable to the selected query element. The system applies the candidate transformation rules to the selected query element to generate a transformed query element that includes a transformed remote query element. If the transformed remote query element is pushdownable, the system adds the transformed remote query element to a transformed inexact query output. Otherwise, the system applies additional candidate transformation rules to the selected query element to generate the transformed inexact query output. The system applies the transformed inexact query output to a heterogeneous datastore to provide an output query result.

Abstract: The invention relates to a system and method for providing efficient policy rule updates in policy-based data management. More particularly, the invention relates to a system and method for restraining the size of the set of data objects to be examined after a policy rule evaluation.

Abstract: A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.

Abstract: A power discharge control system for eliminating residual voltage of electronic components in an electronic device, is proposed, which includes a control IC for outputting first electrical signals of a first level and a second level respectively corresponding to power on and power off of the electronic device; a power supply for receiving the first electrical signal, and providing or terminating operation power to the electronic component accordingly, and delaying outputting of a second electrical signal equivalent to the first electrical signal level; a logic judgment module connected to the control IC and the power supply for receiving the first and the second electrical signals for executing logic operation process, when at least one of the first and the second electrical signals is at the first level, a third electrical signal of a third level is outputted, when both the first and the second electrical signals are at the second level, a third electrical signal of a fourth level is outputted; and at least

Abstract: A virtual binding system ensures that the WORM logic for protecting data immutability cannot be circumvented, effectively guaranteeing WORM property of a WORM storage system composed of rewritable magnetic hard disks. To close the security hole between the rewritable media and the WORM logic, virtual binding securely authenticates the legitimacy of a WORM logic controller before granting data access on a WORM storage media. Furthermore, the system verifies the legitimacy of the WORM logic controller during data access. This approach virtually binds together the WORM logic controller and the WORM storage media even though the WORM logic controller and the WORM storage media may be physically separate.

Abstract: A hydrophobic binding pocket on ubiquitin-protein ligase E3 is described, and used in designing the inhibitors disrupting ubiquitin conjugating enzyme E2 and E3 interaction. Four types of inhibitors designed by using the binding pocket are provided, which can be used for cancer treatment.

Abstract: A virtual binding system ensures that the WORM logic for protecting data immutability cannot be circumvented, effectively guaranteeing WORM property of a WORM storage system composed of rewritable magnetic hard disks. To close the security hole between the rewritable media and the WORM logic, virtual binding securely authenticates the legitimacy of a WORM logic controller before granting data access on a WORM storage media. Furthermore, the system verifies the legitimacy of the WORM logic controller during data access. This approach virtually binds together the WORM logic controller and the WORM storage media even though the WORM logic controller and the WORM storage media may be physically separate.

Abstract: A computer start-up timing control device and a method thereof are provided for generating a power supply signal to enable a power supply unit (PSU) to provide power. The device includes a chipset, a delay circuit, and a logic gate. The delay circuit delays a standby power ready signal of the computer to generate a standby power delay signal. The chipset generates a power supply signal. The standby power delay signal enables the logic gate to transmit the power supply signal to the PSU via the logic gate. The PSU provides a power to make the computer enter a start-up procedure. The standby power delay signal delays the time for the chipset to send a power supply signal, so that a baseboard management controller (BMC) has enough time to complete initialization. Therefore, the chipset is prevented from accessing the BMC and obtaining erroneous information before the BMC finishes initialization.

Abstract: A power discharge control system for eliminating residual voltage of electronic components in an electronic device, is proposed, which includes a control IC for outputting first electrical signals of a first level and a second level respectively corresponding to power on and power off of the electronic device; a power supply for receiving the first electrical signal, and providing or terminating operation power to the electronic component accordingly, and delaying outputting of a second electrical signal equivalent to the first electrical signal level; a logic judgment module connected to the control IC and the power supply for receiving the first and the second electrical signals for executing logic operation process, when at least one of the first and the second electrical signals is at the first level, a third electrical signal of a third level is outputted, when both the first and the second electrical signals are at the second level, a third electrical signal of a fourth level is outputted; and at least