Patents by Inventor Lan-Lin Chao

Lan-Lin Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208607
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11282697
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20210343849
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 4, 2021
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11069785
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11014805
    Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
  • Publication number: 20210151353
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20210013098
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10790189
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10665449
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200006052
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200002161
    Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Application
    Filed: August 19, 2019
    Publication date: January 2, 2020
    Inventors: Chun-wen CHENG, Hung-Chia TSAI, Lan-Lin CHAO, Yuan-Chih HSIEH, Ping-Yin LIU
  • Publication number: 20190259848
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 22, 2019
    Inventors: Chun-Han TSAO, Chi-Ming CHEN, Han-Yu CHEN, Szu-Yu WANG, Lan-Lin CHAO, Cheng-Yuan TSAI
  • Patent number: 10384933
    Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
  • Patent number: 10354972
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 10283448
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10276678
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Publication number: 20190051628
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20190035681
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 31, 2019
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10160638
    Abstract: A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Cheng Chu, Ping-Yin Liu, Xin-Hua Huang, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng
  • Patent number: 10128209
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang