Patents by Inventor Lance Scudder
Lance Scudder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11378511Abstract: A method for detecting corrosion on a conductive object includes submerging a surface of the conductive object at least partially in an aqueous solution, flowing current through the surface of the conductive object by forming a voltage differential across the surface, varying the voltage differential across the surface while monitoring the current through the surface of the conductive object, determining a total charge corresponding to a corrosion level of the surface of the conductive object based on current versus voltage levels. The corrosion level may further be utilized in selecting a cleaning process to remediate the corrosion of the surface based on the corrosion level and in applying a protective corrosion barrier to on at least part of the surface after the cleaning process.Type: GrantFiled: November 21, 2019Date of Patent: July 5, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Gang Grant Peng, Robert Douglas Mikkola, David Britz, Lance Scudder, David W. Groechel
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Patent number: 11355317Abstract: Plasma is generated in a semiconductor process chamber by a plurality of microwave inputs with slow or fast rotation. Radial uniformity of the plasma is controlled by regulating the power ratio of a center-high mode and an edge-high mode of the plurality of microwave inputs into a microwave cavity. The radial uniformity of the generated plasma in a plasma chamber is attained by adjusting the power ratio for the two modes without inputting time-splitting parameters for each mode.Type: GrantFiled: December 13, 2018Date of Patent: June 7, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Satoru Kobayashi, Lance Scudder, David Britz, Soonam Park, Dmitry Lubomirsky, Hideo Sugai
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Patent number: 11348783Abstract: Methods and apparatus provide plasma generation for semiconductor process chambers. In some embodiments, the plasma is generated by a system that may comprise a process chamber having at least two upper microwave cavities separated from a lower microwave cavity by a metallic plate with a plurality of radiation slots, at least one microwave input port connected to a first one of the at least two upper microwave cavities, at least two microwave input ports connected to a second one of the at least two upper microwave cavities, and the lower microwave cavity receives radiation through the plurality of radiation slots in the metallic plate from both of the at least two upper microwave cavities, the lower microwave cavity is configured to form an electric field that provides uniform plasma distribution in a process volume of the process chamber.Type: GrantFiled: September 5, 2019Date of Patent: May 31, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Satoru Kobayashi, Hideo Sugai, Denis Ivanov, Lance Scudder, Dmitry Lubomirsky
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Publication number: 20210156789Abstract: A method for detecting corrosion on a conductive object includes submerging a surface of the conductive object at least partially in an aqueous solution, flowing current through the surface of the conductive object by forming a voltage differential across the surface, varying the voltage differential across the surface while monitoring the current through the surface of the conductive object, determining a total charge corresponding to a corrosion level of the surface of the conductive object based on current versus voltage levels. The corrosion level may further be utilized in selecting a cleaning process to remediate the corrosion of the surface based on the corrosion level and in applying a protective corrosion barrier to on at least part of the surface after the cleaning process.Type: ApplicationFiled: November 21, 2019Publication date: May 27, 2021Inventors: Gang Grant PENG, Robert Douglas MIKKOLA, David BRITZ, Lance SCUDDER, David W. GROECHEL
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Publication number: 20210074539Abstract: Methods and apparatus provide plasma generation for semiconductor process chambers. In some embodiments, the plasma is generated by a system that may comprise a process chamber having at least two upper microwave cavities separated from a lower microwave cavity by a metallic plate with a plurality of radiation slots, at least one microwave input port connected to a first one of the at least two upper microwave cavities, at least two microwave input ports connected to a second one of the at least two upper microwave cavities, and the lower microwave cavity receives radiation through the plurality of radiation slots in the metallic plate from both of the at least two upper microwave cavities, the lower microwave cavity is configured to form an electric field that provides uniform plasma distribution in a process volume of the process chamber.Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Satoru Kobayashi, Hideo Sugai, Denis Ivanov, Lance Scudder, Dmitry Lubomirsky
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Patent number: 10217838Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: April 26, 2018Date of Patent: February 26, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20180261683Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: April 26, 2018Publication date: September 13, 2018Applicant: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 10014387Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: February 18, 2016Date of Patent: July 3, 2018Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9812550Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: January 30, 2017Date of Patent: November 7, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9793172Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: GrantFiled: October 20, 2016Date of Patent: October 17, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Publication number: 20170141209Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20170040225Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Publication number: 20160307907Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.Type: ApplicationFiled: June 3, 2016Publication date: October 20, 2016Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory
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Patent number: 9391076Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.Type: GrantFiled: December 18, 2014Date of Patent: July 12, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory
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Publication number: 20160163823Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9299698Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: June 25, 2013Date of Patent: March 29, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20150340460Abstract: An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1 The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5×1017 dopant atoms per cm3.Type: ApplicationFiled: July 29, 2015Publication date: November 26, 2015Inventors: Lucian Shifren, Pushkar Ranade, Lance Scudder
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Patent number: 9112057Abstract: A method of fabricating a semiconductor device includes providing a substrate having a semiconducting surface and forming a first epitaxial layer on the semiconducting surface. The first epitaxial layer includes a first semiconducting material doped in-situ with at least one dopant of a first conductivity type. The method also includes adding at least one dopant of a second conductivity type into one portion of the substrate to define at least one counter-doped region with an overall doping of the second conductivity type and at least one other region with an overall doping of the first conductivity type in the other portions of substrate. The method further includes forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a second semiconducting material that is substantially undoped.Type: GrantFiled: September 18, 2012Date of Patent: August 18, 2015Assignee: Mie Fujitsu Semiconductor LimitedInventors: Sameer Pradhan, Dalong Zhao, Lingquan Wang, Pushkar Ranade, Lance Scudder
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Patent number: 9105711Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.Type: GrantFiled: December 19, 2013Date of Patent: August 11, 2015Assignee: MIE Fujitsu Semiconductor LimitedInventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
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Patent number: 9041126Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.Type: GrantFiled: September 5, 2013Date of Patent: May 26, 2015Assignee: Mie Fujitsu Semiconductor LimitedInventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim