Abstract: Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.

Abstract: A system for improving the attenuation of an undesired signal found in a differential signal path through the use of inductive coupling. The system includes a primary inductor, a secondary inductor, and a filter. The primary inductor and the secondary inductor operably couple an input differential signal pair to an output differential signal pair, and the filter attenuates an undesired signal in the output differential signal pair.

Abstract: A method for in vivo, ex vivo and in vitro regeneration of cartilage, collagen and bone remodeling by intermittently applied hydrostatic pressure consisting of repeated periods of applied hydrostatic pressure followed and interrupted by periods of recovery. The intermittent hydrostatic pressure is applied at physiological levels 5-10 MPA for an interval of 4 hours followed by a recovery period up to about 20 hours. The interval loading results in the selective inhibition of matrix degrading enzymes, pro-inflammatory cytokines and chemokines that attract inflammatory cells into the joint cavity and in selective decrease of gene expression of growth factors that are inhibitory to type II collagen expression.

Abstract: Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.

Abstract: Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.

Abstract: A bit includes a body portion having a first shape, a first length, a first end and a second end. A collar portion having a second shape, a thickness, a first surface disposed adjacent a second end of the body portion and a second surface forming a ledge for seating against a surface of a rotary cutting head of a mining machine. A shank portion, has a diameter and a second length. A first end of the shank is secured to the second surface of the collar portion. A groove formed around the shaft portion closely adjacent the second end thereof. A bit tip disposed adjacent the first end of the body portion to contact a hard surface. The bit tip tapers to a pointed end. A connecting means is disposed in the groove for connecting the bit to the working machine. A plurality of fins is disposed along an outer surface of the body portion.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: A system for determining image intensity of a radiograph includes an illuminator for providing lighting to the radiograph, an image reference standard having a predetermined color, a digital imaging device for obtaining a digital image of the radiograph and the image reference standard, a computer for receiving and storing the digital image and for executing programs, and an image analysis program being executed on the computer for providing a first image intensity value of a target area in the radiograph and a second image intensity value of the image reference standard and for computing a normalized image intensity value of the target area using the first and second image intensity values. In one embodiment, the image reference standard is an image reference standard of a black color or a white color.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

Abstract: A method of calibrating an apparatus for measuring Radon and/or its progeny in an air sample, includes providing an apparatus for measuring Radon in an air sample that includes a preset offset voltage corresponding to a threshold conductivity value and a preselected reading value for indicating a concentration of Radon and/or its progeny, exposing the apparatus to a calibration area for measuring conductivity of the air therein, comparing the measured conductivity value of the air with the preset offset value for conductivity, and setting a lower threshold conductivity value and corresponding threshold reading value same as the preselected reading value, if the measured conductivity of the air is determined to be lower than the preset offset value for conductivity.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.

Abstract: The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data.

Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

Abstract: Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

Abstract: An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources.