Patents by Inventor Lane A. Smith

Lane A. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and Apparatus for Non-Disruptive Telecommunication Loop Condition Determination
    Publication number: 20130236003
    Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: Agere Systems LLC
    Inventors: Jonathan H. Fischer, Donald R. Laturell, Lane A. Smith
  • Decoupling sampling clock and error clock in a data eye
    Patent number: 8532240
    Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: September 10, 2013
    Assignee: LSI Corporation
    Inventors: Paul Tracy, Mohammad Mobin, Ye Liu, Lane A. Smith
  • CDR with sigma-delta noise-shaped control
    Patent number: 8494092
    Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 23, 2013
    Assignee: LSI Corporation
    Inventors: Vladimir Sindalovsky, Lane Smith, Shawn Logan
  • Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns
    Patent number: 8483266
    Abstract: Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: July 9, 2013
    Assignee: LSI Corporation
    Inventors: Christopher J. Abel, Lane A. Smith, Philip N. Jenkins, Brett D. Hardy, Vladimir Sindalovsky
  • PATTERN DETECTOR FOR SERIALIZER-DESERIALIZER ADAPTATION
    Publication number: 20130142245
    Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Inventors: Vladimir Sindalovsky, Mohammed S. Mobin, Lane A. Smith, Amaresh V. Malipatil, Pervez M. Aziz
  • Method and apparatus for non-disruptive telecommunication loop condition determination
    Patent number: 8437467
    Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 7, 2013
    Assignee: Agere Systems LLC
    Inventors: Jonathan H. Fischer, Donald R. Laturell, Lane A. Smith
  • Method and apparatus for equalization using one or more qualifiers
    Patent number: 8432959
    Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 30, 2013
    Assignee: Agere Systems LLC
    Inventors: Pervez M. Aziz, Mohammad S. Mobin, Gregory W Sheets, Lane A. Smith, Paul H. Tracy
  • Methods and apparatus for detecting and decoding adaptive equalization training frames
    Patent number: 8428195
    Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: April 23, 2013
    Assignee: Agere Systems LLC
    Inventors: Yasser Ahmed, Xingdong Dai, Mohammad S. Mobin, Lane A. Smith
  • Method and apparatus for generating early or late sampling clocks for CDR data recovery
    Patent number: 8407511
    Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: March 26, 2013
    Assignee: Agere Systems LLC
    Inventors: Mohammad S. Mobin, Kenneth W. Paist, Lane A. Smith, Paul H. Tracy, William B. Wilson
  • CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE
    Publication number: 20130070835
    Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 21, 2013
    Inventors: Vladimir Sindalovsky, Lane A. Smith, Brett D. Hardy, Jeffrey S. Kueng
  • Support stand for a two-wheeled pedal vehicle
    Patent number: 8388009
    Abstract: A two-wheeled vehicle comprising a frame, a pair of wheels, and a pedal assembly. The pedal assembly has a sprocket, right crank arm assembly and a left crank arm assembly (the crank arm assemblies include pedals), wherein at least one of the two crank arm assemblies comprises an outer member and an inner member, typically, the inner member being cylindrical at least partially telescopically received in the outer member. Typically one of the inner or outer member is moveable, telescopically between a retracted locked, fixed position and an extended locked, fixed position. In the extended position, the two members lock with respect to each other and allow the bicycle or other two-wheeled vehicle to lay adjacent the support surface on the removed end of the extended member, which extended member typically contains the pedal portion of the pedal assembly.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 5, 2013
    Inventor: Lane A. Smith
  • RESTRICTION OF PROGRAM PROCESS CAPABILITIES
    Publication number: 20130055341
    Abstract: This document describes systems and methods for restricting program process capabilities. In some implementations, the capabilities are restricted by limiting the rights or privileges granted to an application. A plurality of rules may be established for a program, or for a group of programs, denying that program the right to take actions which are outside of the actions needed to implement its intended functionality. A security policy is implemented to test actions initiated in response to an application against the rules to enable decisions restricting the possible actions of the program. Embodiments are disclosed which process the majority of decisions regarding actions against a security profile through use of a virtual machine. In some embodiments, the majority of decisions are resolved within the kernel space of an operating system.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Applicant: Apple Inc.
    Inventors: Simon Cooper, Nick Lane-Smith, Joshua Osborne
  • Methods and apparatus for adapting one or more equalization parameters by reducing group delay spread
    Patent number: 8369470
    Abstract: Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: February 5, 2013
    Assignee: Agere Systems, LLC
    Inventors: Mohammad S. Mobin, Kenneth W. Paist, Lane A. Smith
  • BANG-BANG PHASE DETECTOR WITH HYSTERESIS
    Publication number: 20130009679
    Abstract: In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Inventors: Vladimir Sindalovsky, Lane A. Smith, Jung Cho
  • Methods and apparatus for adaptive link partner transmitter equalization
    Patent number: 8320439
    Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 27, 2012
    Assignee: Agere Systems Inc.
    Inventors: Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Paul H. Tracy
  • Method and apparatus for rate-dependent equalization
    Patent number: 8315298
    Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 20, 2012
    Assignee: Agere Systems Inc.
    Inventors: Pervez M Aziz, Mohammad S Mobin, Gregory W Sheets, Lane A Smith, Paul H. Tracy
  • CDR WITH SIGMA-DELTA NOISE-SHAPED CONTROL
    Publication number: 20120257693
    Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventors: Vladimir Sindalovsky, Lane Smith, Shawn Logan
  • Restriction of program process capabilities
    Patent number: 8272048
    Abstract: This document describes systems and methods for restricting program process capabilities. In some implementations, the capabilities are restricted by limiting the rights or privileges granted to an application. A plurality of rules may be established for a program, or for a group of programs, denying that program the right to take actions which are outside of the actions needed to implement its intended functionality. A security policy is implemented to test actions initiated in response to an application against the rules to enable decisions restricting the possible actions of the program. Embodiments are disclosed which process the majority of decisions regarding actions against a security profile through use of a virtual machine. In some embodiments, the majority of decisions are resolved within the kernel space of an operating system.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: September 18, 2012
    Assignee: Apple Inc.
    Inventors: Simon Cooper, Nick Lane-Smith, Joshua Osborne
  • Method and apparatus for digital VCDL startup
    Patent number: 8219344
    Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Agere Systems Inc.
    Inventors: Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Paul H. Tracy
  • DECOUPLING SAMPLING CLOCK AND ERROR CLOCK IN A DATA EYE
    Publication number: 20120170621
    Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.
    Type: Application
    Filed: January 3, 2011
    Publication date: July 5, 2012
    Inventors: Paul Tracy, Mohammad Mobin, Ye Liu, Lane A. Smith