Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: Methods for synthesizing carbon nanotubes and structures formed thereby, includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access.

Abstract: Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Methods for synthesizing carbon nanotubes and structures formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.

Abstract: A method for synthesizing carbon nanotubes and structure formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.

Abstract: A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the mandrel material for each level of the interconnect structure. The conductive features in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.