Patents by Inventor Larry Clevenger
Larry Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8232211Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.Type: GrantFiled: January 20, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Larry Clevenger, Timothy J. Dalton, Carl J. Radens
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Publication number: 20120190205Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.Type: ApplicationFiled: January 20, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Larry Clevenger, Timothy J. Dalton, Carl J. Radens
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Patent number: 7906426Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: GrantFiled: April 23, 2007Date of Patent: March 15, 2011Assignees: Globalfoundries Singapore Pte. Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Publication number: 20080258308Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: ApplicationFiled: April 23, 2007Publication date: October 23, 2008Inventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Patent number: 7365001Abstract: A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.Type: GrantFiled: December 16, 2003Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Louis L. Hsu, Keith Kwong Hon Wong, Timothy Joseph Dalton, Carl Radens, Larry Clevenger
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Patent number: 7241696Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: GrantFiled: December 11, 2002Date of Patent: July 10, 2007Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 7125792Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: October 24, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Douglas C. La Tulipe, Timothy Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht
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Patent number: 7091612Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: August 15, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Publication number: 20050208742Abstract: A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William America, Larry Clevenger, Andy Cowley, Timothy Dalton, Mark Hoinkis, Kaushik Kumar, Douglas La Tulipe
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Publication number: 20050176237Abstract: In damascene processing, metal hardmask sputtering redeposition that occurs during reactive ion etching (RIE) is exploited to produce, during the RIE process, a desired barrier metal liner on the etched feature.Type: ApplicationFiled: February 5, 2004Publication date: August 11, 2005Inventors: Theodorus Standaert, Bernd Kastenmeier, Yi-Hsiung Lin, Yi-Fang Cheng, Larry Clevenger, Stephen Greco, O Sung Kwon
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Publication number: 20050127511Abstract: A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.Type: ApplicationFiled: December 16, 2003Publication date: June 16, 2005Inventors: Chih-Chao Yang, Louis Hsu, Keith Wong, Timothy Dalton, Carl Radens, Larry Clevenger
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Patent number: 6890815Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.Type: GrantFiled: September 4, 2003Date of Patent: May 10, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Johnathan Faltermeier, Jeremy Stephens, David Dobuzinsky, Larry Clevenger, Munir D. Naeem, Chienfan Yu, Larry Nesbit, Rama Divakaruni, Michael Maldei
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Publication number: 20050077628Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Inventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Publication number: 20050079706Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Inventors: Kaushik Kumar, Douglas La Tulipe, Timothy Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht
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Publication number: 20050051839Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.Type: ApplicationFiled: September 4, 2003Publication date: March 10, 2005Inventors: Johnathan Faltermeier, Jeremy Stephens, David Dobuzinsky, Larry Clevenger, Munir Naeem, Chienfan Yu, Larry Nesbit, Rama Divakaruni, Michael Maldei
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Patent number: 6784105Abstract: A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.Type: GrantFiled: April 9, 2003Date of Patent: August 31, 2004Assignees: Infineon Technologies North America Corp., International Business Machines Corporation, United Microelectronics Co.Inventors: Chih-Chao Yang, Yun Wang, Larry Clevenger, Andrew Simon, Stephen Greco, Kaushik Chanda, Terry Spooner, Andy Cowley, Sunfei Fang
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Publication number: 20040115921Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Staffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 6661097Abstract: In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.Type: GrantFiled: November 1, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Larry Clevenger, Stanley J. Klepeis, Hsiao-Ling Lu, Jeffrey R. Marino, Andrew Herbert Simon, Yun-Yu Wang, Kwong Hon Wong, Chih-Chao Yang
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Patent number: 6420216Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer.Type: GrantFiled: March 14, 2000Date of Patent: July 16, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Larry Clevenger, Louis L. C. Hsu, Chandrasekhar Narayan, Jeremy K. Stephens, Michael Wise
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Patent number: 6361880Abstract: A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling “intermediate” size features in damascene and dual damascene structures.Type: GrantFiled: December 22, 1999Date of Patent: March 26, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Larry Clevenger, Roy C. Iggulden, Rainer F. Schnabel, Stefan Weber