Abstract: Methods and arrangements to attach a QFN to a PCB, systems which include a QFN attached to a PCB, and apparatuses for controlling the deposit of solder upon a PCB are disclosed. Embodiments include transformations, code, state machines or other logic to calculate a total area for the QFN IO pads. Embodiments may then determine a total area for the regions of solder applied to the PCB thermal pad to which the QFN thermal pad may be connected in dependence upon the calculated total area for the QFN IO pads. In some embodiments, the total area of the solder regions applied to the PCB thermal pad is approximately equal to the calculated total area for the QFN IO pads. In many embodiments, the number of regions of solder and the shape of the regions of solder is determined.

Abstract: A multi-chip module and heat-sink cap assembly and method of fabrication, which provides sufficient cooling for higher power density chips. The heat-sink cap has heat-sink columns disposed over each chip on a substrate. The heat-sink columns are interconnected by flexible members to provide a unitary cover. Thin film metallization of at least a portion of the mating surfaces of the substrate, chips and heat-sink column permits soldering of the cap to the chips and substrate to form the package which is a mechanically stable structure with no degradation of interconnection fatigue life due to thermal cycling of the assembly when in use.

Abstract: A multi-chip module and heat-sink cap assembly and method of fabrication, which provides sufficient cooling for higher power density chips. The heat-sink cap has heat-sink columns disposed over each chip on a substrate. The heat-sink columns are interconnected by flexible members to provide a unitary cover. Thin film metallization of at least a portion of the mating surfaces of the substrate, chips and heat-sink column permits soldering of the cap to the chips and substrate to form the package which is a mechanically stable structure with no degradation of interconnection fatigue life due to thermal cycling of the assembly when in use.

Abstract: A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration.