Patents by Inventor Larry D. Kinsman
Larry D. Kinsman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7385298Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component.Type: GrantFiled: July 27, 2006Date of Patent: June 10, 2008Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7321455Abstract: Microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, a method includes placing a plurality of singulated radiation responsive dies on a support member, electrically connecting circuitry of the radiation responsive dies to contacts of the support member, and forming a barrier on the support member between adjacent radiation responsive dies without an adhesive attaching the barrier to the support member. The barrier is formed on the support member after electrically connecting the circuitry of the dies to the contacts of the support member. The barrier can encapsulate at least a portion of the wire-bonds.Type: GrantFiled: July 22, 2005Date of Patent: January 22, 2008Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7285442Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.Type: GrantFiled: February 22, 2005Date of Patent: October 23, 2007Assignee: Micron Technology, Inc.Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
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Patent number: 7282789Abstract: A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the assembly. The semiconductor devices may include semiconductor dice, or they may be devices that have yet to be separated from other devices carried by the same substrates.Type: GrantFiled: September 1, 2004Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7279797Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.Type: GrantFiled: January 3, 2005Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
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Patent number: 7259450Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.Type: GrantFiled: April 25, 2003Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Eugene H. Cloud, Larry D. Kinsman
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Patent number: 7227261Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.Type: GrantFiled: August 26, 2003Date of Patent: June 5, 2007Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden, Terry R. Lee
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Patent number: 7214566Abstract: A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and then dicing the layered assembly. The dielectric layer may be, for example, a flexible tape. The semiconductor devices may be chips containing integrated circuits or memory devices. The dicing operation may be performed by a circular saw or by another suitable apparatus. The chips may be connected to input/output devices, such as ball grid arrays, on the dielectric layer, before the testing and dicing steps. Full wafer testing may be-conducted through the ball grid arrays. A relatively stiff metal sheet may be included in the layered assembly before the testing and dicing steps. The metal material may be used as heat spreaders and/or as electrical ground planes. The chips may be connected to the ball grid arrays by wire bonds or flip chip bumps and vias through the dielectric layer.Type: GrantFiled: June 16, 2000Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Larry D. Kinsman
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Patent number: 7183191Abstract: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.Type: GrantFiled: February 15, 2005Date of Patent: February 27, 2007Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Salman Akram
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Patent number: 7151013Abstract: A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.Type: GrantFiled: October 1, 2002Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Mike Brooks, Mark S. Johnson, Larry D. Kinsman
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Patent number: 7125749Abstract: An integrated circuit package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an integrated circuit die positioned therein. A lead frame, such as a peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes a plurality of leads with portions enclosed within the package body that electrically connect to the integrated circuit die. A heat sink is positioned at least partially within the package body so a surface of a first portion of the heat sink faces the lead frame in close proximity to a substantial part, such as at least eighty percent, of the area of the enclosed portion of the lead frame to thereby substantially reduce an inductance associated with each of the leads.Type: GrantFiled: November 22, 2002Date of Patent: October 24, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Jerry M. Brooks
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Patent number: 7122390Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.Type: GrantFiled: June 14, 2005Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7116001Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.Type: GrantFiled: March 3, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7115990Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.Type: GrantFiled: March 4, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7112252Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.Type: GrantFiled: August 26, 2003Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
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Patent number: 7095122Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component.Type: GrantFiled: September 1, 2004Date of Patent: August 22, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7091622Abstract: A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having at least one conductor thereon. A top insulating layer of the multilayer structure contains a ball grid array. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the insulating material. The metal layer may also be used to dissipate heat from the die. The conductors of the multilayer structure provide additional versatility in wiring the die to the ball grid array.Type: GrantFiled: July 14, 2004Date of Patent: August 15, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Salman Akram
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Patent number: 7082681Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. The stub contacts may be formed by trimming the leads of an existing vertical surface mount package. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.Type: GrantFiled: May 1, 2003Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Walter L. Moden, Warren M. Farnworth
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Patent number: 7057291Abstract: A method for assembling vertically mountable semiconductor devices includes positioning the semiconductor devices so that backsides thereof face one another and that edges of the vertically mountable semiconductor devices along which contacts are disposed are in alignment with each other. The backsides of the vertically mountable semiconductor devices are secured to one another with an adhesive. Individual devices, such as dice, may be positioned and secured to one another in this manner, or larger, multiple-device-carrying substrates, such as device-bearing wafers, may be positioned back-to-back and secured to one another. If the assembled semiconductor devices are carried by larger substrates, individual modules may be subsequently separated from each other.Type: GrantFiled: September 1, 2004Date of Patent: June 6, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 7015063Abstract: A back-to-back semiconductor device module includes two semiconductor devices, the backs of which are secured to one another. Each bond pad of both semiconductor devices is disposed adjacent a single, mutual edge of the module. The module may be oriented nonparallel to a carrier substrate and secured to the carrier substrate directly or indirectly thereto. A module-securing device for indirectly securing the module to the carrier substrate may include an alignment device with one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish electrical connections between the bond pads of the semiconductor devices and corresponding terminals of the carrier substrate. Alternatively, a clip-on lead, one end of which resiliently biases against a lead of at least one of the semiconductor devices, the other end of which is electrically connected to a terminal of the carrier substrate, may be employed as a module-securing device.Type: GrantFiled: May 29, 2002Date of Patent: March 21, 2006Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman