Patents by Inventor Larry D. McMillan
Larry D. McMillan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5559733Abstract: A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.Type: GrantFiled: June 7, 1995Date of Patent: September 24, 1996Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Larry D. McMillan, Takashi Mihara, Hiroyuki Yoshimori, John W. Gregory, Carlos A. Paz de Araujo
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Patent number: 5540772Abstract: A method and apparatus are disclosed for forming thin films of chemical compounds utilized in integrated circuits. The method includes steps of forming a precursor liquid comprising a chemical compound in a solvent, providing a substrate within a vacuum deposition chamber, producing a mist of the precursor liquid, and flowing the mist into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried to form a thin film of a solid material on the substrate, then the integrated circuit is completed to include at least a portion of the film of solid material in a component of the integrated circuit.Type: GrantFiled: October 11, 1994Date of Patent: July 30, 1996Assignee: Symetrix CorporationInventors: Larry D. McMillan, Carlos A. Paz de Araujo, Tommy L. Roberts
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Patent number: 5541870Abstract: A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.Type: GrantFiled: October 28, 1994Date of Patent: July 30, 1996Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Takashi Mihara, Hitoshi Watanabe, Hiroyuki Yoshimori, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 5523964Abstract: An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate.Type: GrantFiled: April 7, 1994Date of Patent: June 4, 1996Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Larry D. McMillan, Takashi Mihara, Hiroyuki Yoshimori, John W. Gregory, Carlos A. Paz de Araujo
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Patent number: 5519234Abstract: An integrated circuit includes a layered superlattice material having the formula A1.sub.w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+ak B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.Type: GrantFiled: November 18, 1993Date of Patent: May 21, 1996Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan
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Patent number: 5514822Abstract: A first metal, an alcohol, and a carboxylic acid are reacted to form a metal alkoxycarboxylate which is then reacted with an alkoxide and/or a carboxylate of a second metal to form a precursor. Alternatively, a metal carboxylate and a metal alkoxide are combined and heated to form a precursor. In either alternative, the precursor includes all or most of the metal-oxygen-metal bonds of a desired metal oxide and a carboxylate ligand. The precursor is applied to a substrate, dried and annealed to form the metal oxide, such as BST. The metal-oxygen-metal bonds in the precursor permit the desired metal oxide to be formed from the precursor in one step, providing excellent thin films suitable for integrated circuits. The carboxylate ligand provides stability to the precursor allowing it to be stored for periods common in large scale manufacturing.Type: GrantFiled: October 6, 1993Date of Patent: May 7, 1996Assignee: Symetrix CorporationInventors: Michael C. Scott, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 5508954Abstract: A method and apparatus for programming ferroelectric memory cells which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Methods and apparatus for producing a signal pulse duty cycle in the range 2-30% is disclosed and shown to improve the useful life of the ferroelectric material.Type: GrantFiled: February 27, 1995Date of Patent: April 16, 1996Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Takashi Mihara, Hitoshi Watanabe, Hiroyuki Yoshimori, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 5487032Abstract: A method and apparatus for programming ferroelectric memory cells which reduces fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the rise AC fall times associated with signals used to switch ferroelectric device polarization are shown to reduce fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), are shown to reduce the fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform, a Gaussian signal waveform, and a waveform having exponential rise and fall times are disclosed.Type: GrantFiled: November 10, 1994Date of Patent: January 23, 1996Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Takashi Mihara, Hitoshi Watanabe, Hiroyuki Yoshimori, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 5468679Abstract: A precursor comprising a medium-length ligand carboxylate, such as a metal 2-ethylhexanoate, in a xylenes solvent is applied to an integrated circuit wafer. The wafer is baked to dry the precursor, annealed to form a layered superlattice material on the wafer, then the integrated circuit is completed.Type: GrantFiled: November 18, 1993Date of Patent: November 21, 1995Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Michael C. Scott, Joseph D. Cuchiaro, Larry D. McMillan
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Patent number: 5468684Abstract: A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.Type: GrantFiled: May 21, 1993Date of Patent: November 21, 1995Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Hiroyuki Yoshimori, Hitoshi Watanabe, Carlos A. Paz De Araujo, Shuzo Hiraide, Takashi Mihara, Larry D. McMillan
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Patent number: 5466629Abstract: An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered.Type: GrantFiled: February 3, 1995Date of Patent: November 14, 1995Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Takashi Mihara, Hiroyuki Yoshimori, Hitoshi Watanabe, Larry D. McMillan, Carlos P. De Araujo
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Patent number: 5463244Abstract: An electrically programmable antifuse element using ferroelectric materials for the insulative dielectric layer, methods for producing same, and an integrated circuit applying a plurality of ferroelectric antifuse elements in a two dimensional matrix of rows and columns for use as a programmable logic device (PLD) or as a programmable read-only memory (PROM). A ferroelectric material is formed between two conductive electrodes to create a ferroelectric antifuse element. In an alternative embodiment, a plurality of chemically distinct materials is layered to form the dielectric layer. The combined application of an AC electric field and a DC electric field breaks down the ferroelectric material to form a low-resistance conductive filament. The synergy of the two electric fields permits programming antifuse elements of the present invention by applying DC electric fields as low as 2 volts amplitude.Type: GrantFiled: May 26, 1994Date of Patent: October 31, 1995Assignee: Symetrix CorporationInventors: Carlos A. P. De Araujo, Larry D. McMillan, Joseph D. Cuchiaro
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Patent number: 5456945Abstract: A method and apparatus are disclosed for forming thin films of chemical compounds utilized in integrated circuits. The method includes steps of forming a precursor liquid comprising a chemical compound in a solvent, providing a substrate within a vacuum deposition chamber, producing a mist of the precursor liquid, and flowing the mist into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried to form a thin film of a solid material on the substrate, then the integrated circuit is completed to include at least a portion of the film of solid material in a component of the integrated circuit.Type: GrantFiled: December 18, 1992Date of Patent: October 10, 1995Assignee: Symetrix CorporationInventors: Larry D. McMillan, Carlos A. Paz de Araujo, Tommy L. Roberts
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Patent number: 5444290Abstract: An antifuse element has a dielectric layer comprising materials whose dielectric constant increases in the presence of a DC electric field, such as a ferroelectric. An applied AC electric field and a DC electric field breaks down the dielectric material to form a conductive filament. The AC electric field causes the physical reorientation of the electric dipole of the molecules in the ferroelectric material which creates heat within the ferroelectric material. The DC electric field enhances the heating effect of the AC electric field by enlarging the electric dipole of the ferroelectric molecules. The synergy of the two electric fields permits programming antifuse elements of the present invention by applying DC electric fields as low as 2 volts amplitude.Type: GrantFiled: May 26, 1994Date of Patent: August 22, 1995Assignee: Symetrix CorporationInventors: Carlos A. Paz De Araujo, Larry D. McMillan, Joseph D. Cuchiaro
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Patent number: 5439845Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.Type: GrantFiled: December 5, 1994Date of Patent: August 8, 1995Assignees: Olympus Optical Co., Ltd., Symetrix CorporationInventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
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Patent number: 5434102Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.Type: GrantFiled: May 21, 1993Date of Patent: July 18, 1995Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
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Patent number: 5423285Abstract: A precursor comprising a metal 2-ethylhexanoate in a xylenes solvent is applied to an integrated circuit wafer. The wafer is baked to dry the precursor, annealed to form a layered superlattice material on the wafer, then the integrated circuit is completed. If the metal is titanium, the precursor comprises titanium 2-methoxyethoxide having at least a portion of its 2-methoxyethoxide ligands replaced by 2-ethylhexanoate. If the metal is a highly electropositive element, the solvent comprises 2-methoxyethanol. If the metal is lead, bismuth, thallium, or antimony, 1% to 75% excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing.Type: GrantFiled: November 24, 1992Date of Patent: June 13, 1995Assignees: Olympus Optical Co., Ltd., Symetrix CorporationInventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan
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Patent number: 5406510Abstract: A non-volatile memory includes a constant voltage source, a bit line, a memory cell having a first ferroelectric capacitor connected between the bit line and the constant voltage source, a source of a reference voltage, and a latch connected between the bit line and the reference voltage. The latch drives the bit line to the same logic state as the ferroelectric capacitor to read and rewrite the capacitor in a single operation. The reference voltage is provided by a ferroelectric dummy capacitor having an area smaller than the area of the first capacitor but greater than 1/2 the area of the first capacitor.Type: GrantFiled: July 15, 1993Date of Patent: April 11, 1995Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Takashi Mihara, Carlos A. Paz De Araujo, Larry D. McMillan
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Patent number: 5316579Abstract: A method and apparatus are disclosed for generating fine mists of liquids using a rotating turbine blade disposed within an enclosure. A mixture of a liquid and a carrier gas are flowed into the enclosure such that it immediately impacts on the rotating turbine blade disposed near a lower end of the enclosure, and the resulting mist is withdrawn under vacuum near an upper end of the enclosure. A method and apparatus are also disclosed for chemical vapor deposition of thin films of complex chemical compounds using the discussed mists.Type: GrantFiled: May 4, 1992Date of Patent: May 31, 1994Assignee: Symetrix CorporationInventors: Larry D. McMillan, Carlos A. Paz de Araujo, Tom L. Roberts
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Patent number: 5138520Abstract: Methods and apparatus for depositing thin films of complex (compound) materials, including ferroelectrics, superconductors, and materials with high dielectric constants by photo/plasma-enhanced chemical vapor deposition from stabilized compound sources. Multiple heating and/or spectral energy sources are used for applying high energy, rapid thermal pulses in a precise timed sequence. Sol-gels of compound sources are ultrasonically atomized before being introduced to the deposition chamber.Type: GrantFiled: June 17, 1991Date of Patent: August 11, 1992Assignee: Symetrix CorporationInventors: Larry D. McMillan, Carlos A. Paz de Araujo