Abstract: An improved distributed processing system for controlling the transfer of data between a terminal controller and a subsystem is described where the improvement insures wordstring consistency in a manner which is completely transparent to the subscriber subsystem. In particular, data is transferred, via a dual-bank, dual-port terminal memory where the bank selection is controlled such that any wordstring transfers between the terminal memory and the terminal controller are constrained to involve a different bank than transfers between the terminal memory and its associated subscriber subsystem. A wordstring log associated with control arbitration logic contains the dynamic state of the bank assignments for each wordstring. Two flag bits in the wordstring log provide information to the control/arbitration logic, allowing it to manage the bank selection of the terminal memory.

Abstract: A method and apparatus allows fault recovery in a digital computer based control system whereby system upsets induced by external transient noise conditions can be accommodated. A CPU is coupled to its main memory and its I/O interfaces by a common address/data bus, these three elements being susceptible to having data thereon or therein corrupted by transient noise. Also coupled to the bus, but in a hardened environment, are first and second supplemental memories which, under memory control, operate on alternating even and odd computational frames defined by the CPU's real-time clock to store the same words as are then being entered into the CPU's main memory. As computational frames are entered into one or the other of these two memories by eaves-dropping on the common bus, the other supplemental memory is transferring its contents to a backup memory which is also housed in the noise-immune environment.

Abstract: A direct memory access (DMA) system with a single bus architecture for controlling data transfers and storage between plural digital processors and plural Input/Output devices. Limiters are included for disabling access to the bus of a processor whose access time exceeds a predetermined time interval. A time governor is included to suppress processor access to the bus when total processor access time in a data communication cycle has exceeded a predetermined time interval. The input and output devices are coupled to the bus through interface isolation circuits that prevent faults in the input and output devices from propagating to the system to cause total system failure. An input or output device fault can only result in erroneous data being provided to a location of the DMA memory reserved for the faulted device. The DMA memory is protected by a Write-Protect Decoding Circuit that prevents processor writing into prohibited areas of the memory.

Abstract: Verification of proper operation of computer programs executing in a central processor and protection of critical data is accomplished by an independent software monitor which accepts data keys from the executing program and outputs defined legitimate codes in response thereto. Legitimate codes and selected portions of input data keys are compared to validate proper softward execution.

Abstract: An automatic flight control system that is software fault tolerant fail operational in response to a first generic failure utilizes two independent subsystems each including a dual channel flight control computer. One channel in each flight control computer includes a digital processor and the other channel includes two digital processors. Cross channel monitoring is included in each flight control computer to discern disagreements between the outputs of the channels. If disagreement occurs between one of the two processing elements in the channel including two processing elements and the processing element of the channel having one processing element, the involved processing element in the two-element channel is disabled. If both processing elements in the two element channel disagree with the processing element in the other channel, the subsystem is disabled. All of the processing elements perform identical tasks.