Abstract: An outboard file cache extended processing complex for use with a host data processing system for providing closely coupled file caching capability is described. Data movers at the host provide the hardware interface to the outboard file cache, provide the formatting of file data and commands, and control the reading and writing of data from the extended processing complex. Host interface adapters receive file access commands sent from the data movers and provide cache access control. Directly coupled fiber optic links couple each of the data movers to the associated one of the host interface adapters and from the nonvolatile memory. A nonvolatile memory to store redundant copies of the cached file data is described. A system interface including bidirectional bus structures and index processors that control the routing of data signals, provides control of storage and retrieval of file cache data derived from host interface adapters and from the nonvolatile memory.

Abstract: A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

Abstract: A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein.

Abstract: A method and apparatus for increasing the efficiency of a dynamic read and/or write operation of a memory element within a computer system. The dynamic read and/or write operation may be performed when the computer system is in a functional mode or a test mode. The present invention may reduce the number of bits that are required to be serially shifted into a design by providing an auto-increment block. It is recognized that most multi-word access to a memory are made to sequential address locations within the memory. The auto-increment block takes advantage of this and automatically manipulates the address thereby not requiring subsequent addresses to be serially shifted into the design. Further, the control word may be stored within the design for subsequent accesses. That is, the support controller may shift a starting address and a control word into the design.

Abstract: A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

Abstract: A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.

Abstract: A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.

Abstract: A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.

Abstract: A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.

Abstract: A system for communicating data between a main processor and a peripheral processor over a fiber optic interface. The interface is a dedicated, point-to-point link operating in full-duplex, asynchronous mode. Dual fibers and physical layer controllers are used in a cascaded fashion to double the throughput of the interface. Frame control logic coordinates formatting of data into frames for transmission over the interface. Frame format and interface protocol are based on FDDI, but are improved to more efficiently transfer data in a point-to-point implementation. Frame Check Sequences are generated and verified to ensure error-free data transfers. Frame sending and frame receiving logic communicate with the main and peripheral processors, accepting data transfer requests and forwarding received data.

Abstract: A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.

Abstract: A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

Abstract: A redundant maintenance architecture for general purpose, digital computer systems. The architecture has both redundant maintenance controllers and redundant maintenance interfaces. This invention provides uninterrupted maintenance control over a distributed system despite any single hardware failure. This is accomplished by providing a low level hardware fault detection and correction apparatus which does not require expensive test hardware or software. The low level hardware apparatus detects faults within a primary maintenance controller or interface and transfer control of the maintenance functions of the computer system to a secondary maintenance controller and interface. All of this is accomplished on-the-fly and does not require that the computer system be switched into a test mode or otherwise interrupted from normal operation.

Abstract: A method and apparatus for identify the source and nature of an error, without aborting the operation of the computer system. In one embodiment of the present invention, the source of the error may be a hardware element and the nature of the error may be identified as either fatal or non-fatal. If the nature of the error is considered non-fatal, the present invention may correct the error and continue the operation of the computer system. This may allow detected errors to be handled immediately after they occur, rather than aborting the operation of the computer system and waiting for a support controller or the like to analyze the error. This may significantly enhance the reliability and performance of a corresponding computer system. This may be especially important during time critical operations. Further, since the operation of the computer system may be aborted a fewer number of times, the present invention may minimize the amount of data loss.

Abstract: A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.

Abstract: A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.

Abstract: A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.

Abstract: A method and system for executing shift, mask, and merge operations on two operands specified by one instruction contains two registers holding operand data and separate shift, mask, and merge logic. A programmer-defined set of mask and merge indicators controls the mask and merge operations. Each mask and merge indicator is represented as a single bit but controls a pair of bits in an operand. If the first operand is selected by the programmer, it is shifted and then masked. The result of the shift and mask operations is merged with the second operand. If the second operand is selected, it is shifted and masked, and the result is merged with the first operand. Final results are stored for processing by subsequent instructions.

Abstract: An apparatus for efficiently testing a plurality of memory devices at the board level. The logic for the present invention is minimal and can be placed on a controller chip within the board design. In addition, the interconnect lines between the controller chip and each of the plurality of memory devices can also be tested. Finally, the present invention requires minimal setup time and performs a functional test of the memories in a very short period of time.

Abstract: A system and method for executing conditional branch instructions by a processor using dynamic branch address tables containing branch target addresses. The branch target addresses are selected by the result of a computation of fields in the branch instruction and an index generated during the execution of previous instructions. The relevant fields include the base address of a branch address table and a mask value. The contents, size, and location of the branch address tables in a random-access-memory local store may be changed during run-time by program control.