Abstract: In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs to provide a soft symbol confidence level. Simultaneously with calculating the difference between two potential next state accumulated costs, performing a compare-select operation to identify one of the two potential next state accumulated costs as an extremum of the two present state accumulated costs.

Abstract: There is disclosed, a method and apparatus for processing a signal in a pipeline. The method includes retrieving a present state cost. Simultaneously with receiving the present state cost, an estimated symbol and a received symbol are obtained, a difference between the received and estimated symbols is found, the difference between the received and esitmated symbols is squared, and the present state cost is added to the squared difference to generate a next state cost. The apparatus includes hardware to carry out the method.

Abstract: There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the sign of an input to a second adder with a first input to generate a first potential sum. A second adder operating in parallel with the first adder combines first, second and third inputs to generate a second potential sum. An overflow detector combines the first and second inputs of the second adder to determine if there is an overflow. If an overflow is not present, a multiplexer selects the output of the second adder as the output to be saturated. If an overflow is present, the multiplexer selects the output from the first adder as the output to be saturated.

Abstract: A truncated product partial canonical signed digit (PCSD) multiplier is disclosed for use in a finite impulse response (FIR) digital filter. Each multiplier quantity is coded as two non-zero signed digits in an 8-bit word. Each non-zero signed digit is recoded into a four bit nibble for application to the multiplier. Each partial product output of the multiplier is truncated from 16 to 11 bits. The multiplier operations are performed in the sequence shift right, truncate, one's complement, add partial products and, according to the output of a logic control circuit, add one into an appropriate order.