Abstract: A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner.

Abstract: Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer, thereby simplifying the formation of the trench isolating structure, and enabling the substrate to be polished substantially flush with the trench fill. The planar trench fill-substrate interface avoids additional topography, thereby facilitating application of, and enhancing the accuracy of, photolithographic techniques in forming features with minimal dimensions.

Abstract: A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.

Abstract: An RF transceiver operable in two separate frequency bands has transmitter and receiver elements with broadband components to provide a flat frequency response across the two separate operating frequency bands. The broadband transmitting and receiving elements are utilized with other narrow band components which are designed for operating in either the first frequency band or the second frequency band. The use of common components for operating in both frequency bands reduces part count and cost along with reduced size and weight.

Abstract: A differential input buffer operable at power supply voltages below 3.0 V comprises first and second field effect transistors connected between a power supply and a current source as a differential pair in receiving input and input bar signals. Using enhancement mode field effect transistors and heterojunction bipolar transistors for a current source, a power supply voltage Vcc as low as 2 V is possible for circuit operation.

Abstract: A low voltage regulator integrated circuit for high speed/high frequency circuits incorporates a field effect transistor switch with a heterojunction bipolar transistor in order to reduce voltage requirements of the circuit and allow lower power voltages to be regulated. A first field effect transistor connects an unregulated power input terminal to a regulated power output terminal with a bias circuit including the heterojunction bipolar transistor provided to maintain conductance of the field effect transistor in regulating a voltage on the output terminal. A second field effect transistor can be included in the circuit to provide a power down or power saving mode of operation. An input voltage range of the voltage regulator is reduced from 3-3.5 V to 2-2.3 V using the integrated field effect transistor/heterojunction bipolar transistor device structure.