Patents by Inventor Larry Wissel
Larry Wissel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090067270Abstract: A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.Type: ApplicationFiled: May 7, 2008Publication date: March 12, 2009Applicant: International Business Machines CorporationInventor: Larry Wissel
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Publication number: 20090067269Abstract: A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.Type: ApplicationFiled: September 12, 2007Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Larry Wissel
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Publication number: 20080201675Abstract: A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop.Type: ApplicationFiled: April 29, 2008Publication date: August 21, 2008Applicant: International Business Machines CorporationInventor: Larry Wissel
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Publication number: 20080071489Abstract: An integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Applicant: International Business Machines CorporationInventor: Larry Wissel
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Patent number: 7345943Abstract: An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.Type: GrantFiled: June 28, 2006Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventor: Larry Wissel
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Publication number: 20080002450Abstract: An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.Type: ApplicationFiled: June 28, 2006Publication date: January 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Larry Wissel
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Patent number: 7315193Abstract: Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.Type: GrantFiled: August 24, 2005Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Darren L. Anand, Larry Wissel
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Publication number: 20070250797Abstract: A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.Type: ApplicationFiled: April 24, 2006Publication date: October 25, 2007Inventors: James Engel, Susan Lichtensteiger, Paul Sulva, Larry Wissel
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Publication number: 20070046361Abstract: Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.Type: ApplicationFiled: August 24, 2005Publication date: March 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Darren Anand, Larry Wissel
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Patent number: 7098721Abstract: An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.Type: GrantFiled: September 1, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Michael R. Ouellette, Larry Wissel
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Publication number: 20060059393Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.Type: ApplicationFiled: November 8, 2005Publication date: March 16, 2006Inventors: Jeffrey Oppold, Michael Ouellette, Larry Wissel
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Publication number: 20060044049Abstract: An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.Type: ApplicationFiled: September 1, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Ouellette, Larry Wissel
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Patent number: 7000155Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.Type: GrantFiled: April 21, 2003Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Jeffery H. Oppold, Michael R. Ouellette, Larry Wissel
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Publication number: 20040210802Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.Type: ApplicationFiled: April 21, 2003Publication date: October 21, 2004Applicant: International Business Machines CorporationInventors: Jeffery H. Oppold, Michael R. Ouellette, Larry Wissel
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Patent number: 6624677Abstract: A flip-flop circuit comprising: a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data.Type: GrantFiled: July 8, 2002Date of Patent: September 23, 2003Assignee: International Business Machines CorporationInventor: Larry Wissel
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Patent number: 6609228Abstract: A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.Type: GrantFiled: November 15, 2000Date of Patent: August 19, 2003Assignee: International Business Machines CorporationInventors: Paul H. Bergeron, Keith M. Carrig, Alvar A. Dean, Roger P. Gregor, David J. Hathaway, David E. Lackey, Harold E. Reindel, Larry Wissel
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Publication number: 20030115555Abstract: A method and apparatus for implementing Boundary-Scan functionality (i.e. the selection of either functional or test data) while eliminating undesirable delay during the selection of the functional data.Type: ApplicationFiled: November 12, 1999Publication date: June 19, 2003Inventor: LARRY WISSEL
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Patent number: 6490708Abstract: A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created.Type: GrantFiled: March 19, 2001Date of Patent: December 3, 2002Assignee: International Business Machines CorporationInventors: John M. Cohn, Scott W. Gould, Peter A. Habitz, Jose L. P. Neves, William F. Smith, Larry Wissel, Paul S. Zuchowski
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Publication number: 20020133791Abstract: A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created.Type: ApplicationFiled: March 19, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: John M. Cohn, Scott W. Gould, Peter A. Habitz, Jose L. P. Neves, William F. Smith, Larry Wissel, Paul S. Zuchowski
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Patent number: 6426641Abstract: An oscillator circuit on a chip with a single I/O node whose output generally corresponds to a performance level of the IC chip. The single I/O node provides an easy access and testing point for evaluating chip performance. The I/O node is used for coupling to the oscillator circuit, and for activating and monitoring its oscillating output signal. The single I/O node may be accessed at the wafer level, after packaging, or in the field.Type: GrantFiled: October 21, 1998Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Steven P. Koch, Donald L. Wheater, Larry Wissel