Abstract: A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/D structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a first lower semiconductor device having one or more first lower channels and first lower work function metal (WFM) covering the first lower channels, and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first upper semiconductor device can have one or more first upper channels and first upper WFM covering the first upper channels. The semiconductor structure can also include a monolayer formed on dielectric surfaces of the semiconductor structure, and an isolation dielectric deposited on the first lower WFM and between the first lower semiconductor device and the first upper semiconductor device to isolate the first lower semiconductor device from the first upper semiconductor device.

Abstract: In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Abstract: A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

Abstract: A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

Abstract: An integrated circuit product including a first layer of insulating material that includes a first insulating material, a metallization blocking structure positioned in an opening in the first layer of insulating material, a second layer of insulating material including a second insulating material positioned below the metallization blocking structure, a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure, and a conductive metallization line positioned in the metallization trench on opposite sides of the metallization blocking structure.

Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

Abstract: A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.