Patents by Inventor Lars Liebmann

Lars Liebmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013111
    Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Kandabara TAPILY, Lars LIEBMANN, Daniel CHANEMOUGAME, Mark GARDNER, H. Jim FULFORD, Anton J. DEVILLIERS
  • Publication number: 20200381430
    Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.
    Type: Application
    Filed: April 15, 2020
    Publication date: December 3, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers, Daniel Chanemougame
  • Publication number: 20200373330
    Abstract: A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.
    Type: Application
    Filed: December 17, 2019
    Publication date: November 26, 2020
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Publication number: 20200373203
    Abstract: A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.
    Type: Application
    Filed: December 19, 2019
    Publication date: November 26, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Patent number: 10796056
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Publication number: 20200266169
    Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 20, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Hoyoung KANG, Lars LIEBMANN, Jeffrey SMITH, Anton DEVILLIERS, Daniel CHANEMOUGAME
  • Patent number: 10699942
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven Soss, Lars Liebmann, Hui Zang, Shesh Mani Pandey
  • Publication number: 20200194306
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Patent number: 10685874
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Publication number: 20200135718
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 30, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Publication number: 20200075489
    Abstract: A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Publication number: 20200075592
    Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Publication number: 20190392106
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Patent number: 10497798
    Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Bentley, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann, Su Chen Fan, Brent Anderson
  • Patent number: 10468300
    Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andre Labonte, Lars Liebmann, Daniel Chanemougame, Chanro Park, Nigel Cave, Vimal Kamineni
  • Publication number: 20190326286
    Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul Paul, Lars Liebmann
  • Publication number: 20190326165
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven Soss, Lars Liebmann, Hui Zang, Shesh Mani Pandey
  • Publication number: 20190287863
    Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Edward J. Nowak, Julien Frougier, Jia Zeng
  • Patent number: 10418484
    Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Edward J. Nowak, Julien Frougier, Jia Zeng
  • Patent number: 10411010
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave