Abstract: A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth.

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

Abstract: A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

Abstract: Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can include forming multilayer stacks on separate substrates and forming bonding films over the multilayer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multilayer stacks. The method can be repeated to form additional combinations. In between iterations, transistor devices may be formed from the combined structures. Ionized atom implantation can facilitate cleavage of a substrate destined for growth of additional multilayers, wherein an anneal weakens the substrate at a predetermined penetration depth of the ionized atom implantation.

Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth.

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a first stack of transistors and a second stack of transistors. The first stack includes a first transistor and a second transistor stacked on the first transistor along a Z direction perpendicular to a substrate plane. The second stack includes a third transistor and a fourth transistor stacked on the third transistor along the Z direction. The semiconductor apparatus includes a first routing track and a second routing track electrically isolated from the first routing track. The first and second routing tracks extend in an X direction parallel to the substrate plane. A first and fourth conductive trace conductively couple a first gate of the first transistor and a fourth gate of the fourth transistor to the first routing track, respectively. A first terminal structure conductively couples four source/drain terminals of the first, second, third and fourth transistors, respectively.

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

Abstract: A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.

Abstract: A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.