Patents by Inventor Laura Mirkarimi
Laura Mirkarimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892252Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: GrantFiled: March 2, 2020Date of Patent: January 12, 2021Assignee: XCELSIS CORPORATIONInventors: Eric M. Nequist, Steven L. Teig, Javier DeLaCruz, Ilyas Mohammed, Laura Mirkarimi
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Publication number: 20200203318Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Eric M. Nequist, Steven L. Teig, Javier DeLaCruz, Ilyas Mohammed, Laura Mirkarimi
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Patent number: 10580757Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: GrantFiled: May 10, 2018Date of Patent: March 3, 2020Assignee: Xcelsis CorporationInventors: Eric M. Nequist, Steven L. Teig, Javier DeLaCruz, Ilyas Mohammed, Laura Mirkarimi
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Publication number: 20180331072Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: ApplicationFiled: May 10, 2018Publication date: November 15, 2018Inventors: Eric M. Nequist, Steven L. Teig, Javier DeLaCruz, Ilyas Mohammed, Laura Mirkarimi
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Patent number: 9691679Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).Type: GrantFiled: May 19, 2016Date of Patent: June 27, 2017Assignee: Invensas CorporationInventors: Reynaldo Co, Laura Mirkarimi
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Publication number: 20160260647Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).Type: ApplicationFiled: May 19, 2016Publication date: September 8, 2016Inventors: Reynaldo Co, Laura Mirkarimi
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Patent number: 9349706Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).Type: GrantFiled: February 14, 2013Date of Patent: May 24, 2016Assignee: Invensas CorporationInventors: Reynaldo Co, Laura Mirkarimi
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Publication number: 20150017765Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).Type: ApplicationFiled: February 14, 2013Publication date: January 15, 2015Applicant: INVENSAS CORPORATIONInventors: Reynaldo Co, Laura Mirkarimi
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Patent number: 8853558Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.Type: GrantFiled: December 10, 2010Date of Patent: October 7, 2014Assignee: Tessera, Inc.Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
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Patent number: 8772152Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.Type: GrantFiled: January 29, 2013Date of Patent: July 8, 2014Assignee: Invensas CorporationInventors: Reynaldo Co, Laura Mirkarimi
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Patent number: 8680662Abstract: A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.Type: GrantFiled: June 15, 2009Date of Patent: March 25, 2014Assignee: Tessera, Inc.Inventors: Belgacem Haba, Ilyas Mohammed, Laura Mirkarimi, Moshe Kriman
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Patent number: 8461672Abstract: A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements (12, 12A) each having a front surface (117), contacts (22) exposed at the front surface, a rear surface (118) and edges (18, 20) extending between the front and rear surfaces. Traces (24) connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face (90) of the microelectronic unit. A plurality of conductors (66) may extend along edges of the microelectronic elements from the traces (24) to the top face (90). The conductors may be conductively connected with unit contacts (76) such that the unit contacts overlie the rear surface (118) of the at least one microelectronic element (12A) adjacent to the top face.Type: GrantFiled: July 25, 2008Date of Patent: June 11, 2013Assignee: Tessera, Inc.Inventors: Belgacem Haba, Giles Humpston, David Ovrutsky, Laura Mirkarimi
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Patent number: 8372741Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.Type: GrantFiled: February 24, 2012Date of Patent: February 12, 2013Assignee: Invensas CorporationInventors: Reynaldo Co, Laura Mirkarimi
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Publication number: 20120145442Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicant: TESSERA RESEARCH LLCInventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
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Patent number: 8076788Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.Type: GrantFiled: November 8, 2010Date of Patent: December 13, 2011Assignee: Tessera, Inc.Inventors: Belgacem Haba, Ilyas Mohammed, Vage Oganesian, David Ovrutsky, Laura Mirkarimi
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Publication number: 20110006432Abstract: A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements (12, 12A) each having a front surface (117), contacts (22) exposed at the front surface, a rear surface (118) and edges (18, 20) extending between the front and rear surfaces. Traces (24) connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face (90) of the microelectronic unit. A plurality of conductors (66) may extend along edges of the microelectronic elements from the traces (24) to the top face (90). The conductors may be conductively connected with unit contacts (76) such that the unit contacts overlie the rear surface (118) of the at least one microelectronic element (12A) adjacent to the top face.Type: ApplicationFiled: July 25, 2008Publication date: January 13, 2011Applicant: TESSERA, INC.Inventors: Belgacem Haba, Giles Humpston, David Ovrutsky, Laura Mirkarimi
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Publication number: 20090316378Abstract: A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.Type: ApplicationFiled: June 15, 2009Publication date: December 24, 2009Applicant: Tessera Research LLCInventors: Belgacem Haba, Ilyas Mohammed, Laura Mirkarimi, Moshe Kriman
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Publication number: 20060210425Abstract: In accordance with the invention, a method of making a device having improved surface properties is provided. The subject method involves contacting a surface of a device with a vaporized inorganic compound under conditions suitable for production of an inorganic coating on the surface, where the surface is a dielectric surface of an optical component or a sample-contact surface of a device adapted to be contacted with an analyte-containing sample. Also provided are devices having a vapor deposited inorganic coating, as well as methods of using such devices.Type: ApplicationFiled: March 21, 2005Publication date: September 21, 2006Inventor: Laura Mirkarimi
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Publication number: 20060029347Abstract: A two-dimensional photonic crystal resonator apparatus in which the power of light coupled out of the apparatus in one direction is greater than the power of light coupled out of the apparatus in the opposite direction The apparatus has a photonic crystal slab waveguide structure having a waveguide and a resonator in the vicinity of the waveguide such that light propagated through the waveguide is extracted from the waveguide through the resonator and is coupled out of the plane of the apparatus. The apparatus has upper and lower cladding layers on the photonic crystal slab waveguide structure having different indices of refraction, and the power of light coupled out of the apparatus in the direction of the cladding layer having the higher index of refraction is greater than the power of the light coupled out of the apparatus in the direction of the cladding layer having the lower index of refraction.Type: ApplicationFiled: August 3, 2004Publication date: February 9, 2006Inventors: Mihail Sigalas, Annette Grot, Laura Mirkarimi
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Patent number: 6993234Abstract: A two-dimensional photonic crystal resonator apparatus in which the power of light coupled out of the apparatus in one direction is greater than the power of light coupled out of the apparatus in the opposite direction The apparatus has a photonic crystal slab waveguide structure having a waveguide and a resonator in the vicinity of the waveguide such that light propagated through the waveguide is extracted from the waveguide through the resonator and is coupled out of the plane of the apparatus. The apparatus has upper and lower cladding layers on the photonic crystal slab waveguide structure having different indices of refraction, and the power of light coupled out of the apparatus in the direction of the cladding layer having the higher index of refraction is greater than the power of the light coupled out of the apparatus in the direction of the cladding layer having the lower index of refraction.Type: GrantFiled: August 3, 2004Date of Patent: January 31, 2006Assignee: Agilent Technologies, Inc.Inventors: Mihail Sigalas, Annette Grot, Laura Mirkarimi