Abstract: An integrated circuit chip having improved on-chip circuitry including a phase-locked-loop for providing accurately timed signal having different durations and differently occurring timing edges.

Abstract: A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide.

Abstract: High speed instruction execution apparatus is disclosed which provides multistage pipelining and branch prediction in a manner which permits speculative changes of state to be made during execution of a predicted instruction before the correctness of the prediction has been determined.

Abstract: An IC chip employs a common multiplexor logic element in different logic configurations for performing a variety of different logic functions, whereby path delays can be accurately matched. In addition, a phase-locked-loop is employed for providing accurately timed signals having different durations and differently occurring timing edges.

Abstract: A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area. A still further enhancement in multiplier operating speed is achieved by providing connections to adders so as to take advantage of the different times of arrival of the inputs to each level along with different adder input-to-output delays.

Abstract: An integrated circuit chip on which a relatively large on-chip delay is provided using a relatively small delay in conjunction with a phase-locked-loop, whereby the relatively large variations typical of large on-chip delays are avoided.

Abstract: A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area.

Abstract: A digital adder module has a carry-in terminal, N pairs of data terminals, N sum terminals, and a carry-out terminal. A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel plus one transistor drain plus one internal logic gate plus interconnections between them.

Abstract: A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations.

Abstract: A multiplicity of independently operating disk drive subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk drive subsystems via the error circuitry such that the overall system appears as a large, high capacity disk drive system having an unusually high fault tolerance and a very high bandpass. Caching is additionally provided in the read/write interface in a manner which takes advantage of the organization provided by the data organizer to significantly improve overall performance. Advantage is also taken of the conventionally provided error detection capability of each disk drive subsystem to enhance the capability of the error circuitry.

Abstract: An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be written with new instruction data from a fetch module while a previously written page is concurrently being read by the execute module for execution of a designated data processing operation. When the execute module completes execution and requires a new block of data, the two pages are logically switched by toggling an address bit.

Abstract: Apparatus for providing automatic clock de-skewing for a plurality of circuit boards of a data processing system. In a preferred embodiment, each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board. In a preferred implementation of the clock de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate reference delay are employed in conjunction with a phase comparator for automatically providing de-skewed clocks at the clock outputs of the clock distribution chip. The accurate reference delay is advantageously provided by a strip transmission line formed in a conductive layer of the multi-layer board containing the chips.

Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.

Abstract: A relatively large plurality of relatively small, independently operating disk subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk subsystems via the error circuitry such that the overall system appears as a large, high capacity disk system having an unusually high fault tolerance and a very high bandpass.

Abstract: On-line timing signal fault detection is provided by taking advantage of differential signal distribution commonly employed in digital data processing systems. An acceptance window indicative of permissible phase shift variations between the differential signals is established using a plurality of flip-flops having clock and data inputs to which delayed, undelayed, inverted and uninverted versions of the differential signals are applied in a predetermined manner. Also included is the capability of providing fault detection even when one of the differential signals is lost.

Abstract: A method for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, the method is employed to de-skew the clock outputs provided by a plurality of clock distribution chips having different signal propagation times. In a preferred implementation of the method, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Abstract: Apparatus for automatically adjusting the propagation time delay of an electrical circuit, such as an integrated circuit chip. In a preferred embodiment, automatic de-skewing circuitry is provided on each of a plurality of clock distribution chips for de-skewing the clock outputs from different chips. In a preferred implementation of the de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate constant delay are employed in conjunction with a phase comparator for automatically adjusting the propagation delay of each chip to provide substantially the same constant delay relative to a main system clock for the clock outputs provided by the clock distribution chips.

Abstract: Apparatus is disclosed which provides for testing a wide variety of different types of electrical circuit devices, such as PROM integrated circuit chips, with very little if any programming being required, and without concern as to which of the terminals of the chip are inputs or outputs. The testing apparatus achieves this result by taking advantage of the significant difference in the input and output impedances of most chips to permit treating the logical levels on both inputs and outputs of the chip in a like manner while generating a running signature output in response to a series of input test patterns, the resulting final signature obtained being indicative of the operation of the chip. Provision is also made for testing circuits having internal storage and/or requiring special power or clock inputs.

Abstract: Methods are disclosed which provide for testing a wide variety of different types of electrical circuit devices, such as PROM integrated circuit chips, with very little if any programming being required, and without concern as to which of the terminals of the chip are inputs or outputs. The testing apparatus achieves this result by taking advantage of the significant difference in the input and output impedances of most chips to permit treating the logical levels on both inputs and outputs of the chip in a like manner while generating a running signature output in response to a series of input test patterns, the resulting final signature obtained being indicative of the operation of the chip. Provision is also made for testing circuits having internal storage and/or requiring special power or clock inputs.

Abstract: N-way microprogram branching is employed in conjunction with a specially organized multiple-chip microinstruction memory in a manner which makes it possible to divide the accessing of the memory into two separate operations which can be performed simultaneously and in parallel, thereby significantly reducing the time required for accessing the memory.