Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.

Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an initial format and in an initial organizational arrangement. The processing thread will then store data within this portion of the initial results data belonging to a target category of the desired output organizational arrangement, such as a cell, at a memory location corresponding to that target category. It will also convert the stored data from a first data format to another data format for output. The first data format may use a relatively low amount of compression, with the second data format may use a relatively high level of compression.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses).