Abstract: The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.

Abstract: The invention relates to a method of fabricating an electromechanical structure presenting a first substrate (1) including at least one layer (1?) of monocrystalline material covered in a sacrificial layer (2) that presents a free surface, the structure presenting at least one mechanical reinforcing pillar received in said sacrificial layer, the method being characterized in that it comprises: a) making at least one well region (51, 52) in the sacrificial layer (2) by etching, at least in the entire thickness of the sacrificial layer (2), the well region defining at least one said mechanical pillar; b) depositing a first functionalization layer (4, 31) of a first material, relative to which the sacrificial layer is suitable for being etched selectively, the functionalization layer (4) filling at least one well region (51) at least partially and covering the free surface of the sacrificial layer (2) at least around the well region(s); and b?) depositing a filler layer (6, 32) of a second material different

Abstract: The invention relates to a method of fabricating an electromechanical device including an active element, wherein the method comprises the following steps: a) making a monocrystalline first stop layer on a monocrystalline layer of a first substrate; b) growing a monocrystalline mechanical layer epitaxially on said first stop layer out of at least one material that is different from that of the stop layer; c) making a sacrificial layer on said active layer out of a material that is suitable for being etched selectively relative to said mechanical layer; d) making a bonding layer on the sacrificial layer; e) bonding a second substrate on the bonding layer; and f) eliminating the first substrate and the stop layer to reveal the surface of the mechanical layer opposite from the sacrificial layer, the active element being made by at least a portion of the mechanical layer.

Abstract: A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.

Abstract: A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.

Abstract: The invention relates to a method for manufacturing an SOI substrate, associating silicon based areas and areas of GaAs based material at the thin layer of the SOI substrate, the SOI substrate comprising a silicon support supporting successively a layer of dielectric material and a thin layer of silicon.

Abstract: A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0<y?1) that have different respective Germanium contents.

Abstract: The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.

Abstract: A data storage medium includes a carrier substrate having an electrode layer on the surface,and a sensitive material layer extending along the electrode layer, the volume whereof is adapted to be locally modified between two electrical states by the action of a localized electric field. A reference plane extends globally parallel to the sensitive material layerand is configured to pass along it at least one element for application of an electrostatic field in combination with the electrode layer. The storage medium also includes, parallel to the reference plane, a plurality of conductive portions forming part of the electrode layer and separated by at least one electrically insulative zone, the electrically conductive portions having, in at least one direction parallel to the reference plane, a dimension at most equal to 100 nm, where at least some of the conductive portions are electrically interconnected, the conductive portions defining data write/read locations within the sensitive material layer.

Abstract: A method of transferring a thin film onto a first support, includes supplying a structure comprising a film of which at least one part originates from a solid substrate of a first material and which is solidly connected to a second support having a thermal expansion coefficient that is different from that of the first material and close to that of the first support, forming an embrittled area inside the film that defines the thin film to be transferred, affixing the film that is solidly connected to the second support to the first support, and breaking the film at the embrittled area.

Abstract: The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric field in the intermediate zone (I), on the same side as the first junction (3), and a second gate (6) to generate an electric field in the intermediate zone (I), on the same side as the second junction (4).

Abstract: The method includes the following steps: supplying a substrate comprising a support having one face made of a dielectric material supporting a strained silicon thin layer having a <110> or <111> orientation, formation of a first mask on a portion of the strained silicon thin layer, epitaxy of Si1?xGex on the portion of the layer not masked by the first mask, germanium condensation, until a strained germanium layer is obtained, which rests on the face of the support made of a dielectric material, the strained germanium layer then being covered by a silicon oxide layer, elimination of the first mask and of the silicon oxide layer, formation of a second mask on said semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the remaining strained germanium portion and at least one region of the strained silicon portion, the second mask exposing a remaining strained germanium portion, epitaxial growth of germanium on the remaining strained germanium portion, in

Abstract: A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed.

Abstract: The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.

Abstract: Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.

Abstract: The invention relates to a method for manufacturing an SOI substrate, associating silicon based areas and areas of GaAs based material at the thin layer of the SOI substrate, the SOI substrate comprising a silicon support supporting successively a layer of dielectric material and a thin layer of silicon.

Abstract: The disclosure relates a method for producing a microelectronic device including a plurality of based Si1-yGey semi-conductor zones (where 0<y?1) have different respective Germanium contents, comprising the steps of: a) formation on a plurality of Si based semi-conductor zones with different thicknesses resting on a substrate, of a Si1-yGey based semi-conductor layer (where 0<x<1 and x<y), b) oxidation of the Si1-yGey based semi-conductor layer.

Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0<y?1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si1-yGey based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.