Abstract: A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.

Abstract: Disclosed is a method for grinding a hydraulic binder, including: a) introducing:—a hydraulic binder, and—a composition B including at least one grinding aid B into the first chamber of a horizontal grinder including several chambers, including a first chamber and a last chamber, each chamber being separated from the adjacent chamber by a diaphragm, whereby a composition ? including the hydraulic binder and composition B is obtained in the first chamber; and b) grinding composition ? in the horizontal grinder, whereby composition ? moves from the first chamber to the last chamber and a ground composition C is obtained at the outlet of the last chamber. At the grinding step, the method includes introducing into the last chamber a composition A including at least one grinding aid A including an aminoalcohol. Also disclosed is a corresponding grinding unit.

Abstract: A half-bridge electronic device comprises a high level switch and a low level switch in series that are connected at a central point, and a first and a second synchronization system: • the first system comprising a first detection circuit configured to interpret a variation, following a falling edge, of the voltage (Vm) at the central point, and the first system being configured to generate a first synchronization signal (ATON-LS) for activating the low level switch; • the second system comprising a second detection circuit configured to interpret a variation, following a rising edge, of the voltage (Vm) at the central point, and the second system being configured to generate a second synchronization signal (ATON-HS) for activating the high level switch.

Abstract: A power circuit switching device comprises two switching terminals, a high-voltage depletion mode transistor and a low-voltage enhancement mode transistor arranged in series between the two switching terminals, a first terminal for receiving a switching signal and electrically connected via a driver circuit to the gate of the high-voltage transistor, and a second terminal for receiving a control signal and electrically connected to the gate of the low-voltage transistor. The device comprises a normally-on protection circuit electrically connected between the second terminal and the gate of the high-voltage transistor to keep the high-voltage transistor in an off-state when the driver circuit is not electrically powered.

Abstract: A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.

Abstract: A half-bridge electronic device comprises a high level switch and a low level switch in series that are connected at a central point, and a first and a second synchronization system: •the first system comprising a first detection circuit configured to interpret a variation, following a falling edge, of the voltage (Vm) at the central point, and the first system 040-being configured to generate a first synchronization signal (ATON-LS) for activating the low level switch; •the second system comprising a second detection circuit configured to interpret a variation, following a rising edge, of the voltage (Vm) at the central point, and the second system being configured to generate a second synchronization signal (ATON-HS) for activating the high level switch.

Abstract: A switching device of a load comprises: two switching terminals; a depletion-mode high-voltage transistor and an enhancement-mode low-voltage transistor arranged in series between the two switching terminals and defining a midpoint; a control circuit generating a control signal of the gate of the low-voltage transistor in order to selectively place the device in an on state or in an off state; a power-supply circuit comprising an input connected to the midpoint and an output for supplying a power voltage to the control circuit. The power-supply circuit comprises a reservoir capacitance connected to a normally-on switch for charging the reservoir capacitance and supplying the power voltage to the control circuit when the switching device is connected to the load.

Abstract: A power circuit switching device comprises two switching terminals, a high-voltage depletion mode transistor and a low-voltage enhancement mode transistor arranged in series between the two switching terminals, a first terminal for receiving a switching signal and electrically connected via a driver circuit to the gate of the high-voltage transistor, and a second terminal for receiving a control signal and electrically connected to the gate of the low-voltage transistor. The device comprises a normally-on protection circuit electrically connected between the second terminal and the gate of the high-voltage transistor to keep the high-voltage transistor in an off-state when the driver circuit is not electrically powered.

Abstract: An integrated circuit comprises a housing, a plurality of connection pins, a first chip that includes a high-voltage depletion mode transistor, and a second chip that includes a low-voltage enhancement mode transistor. The first chip and second chip each comprise a gate bump contact, a drain bump contact and a source bump contact. The source bump contact of the high-voltage transistor is electrically connected to the drain bump contact of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin that is electrically connected to the source bump contact of the low-voltage transistor.

Abstract: An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.

Abstract: A power circuit switching device includes two switching terminals; a high voltage depletion mode transistor and a low voltage enhancement mode transistor arranged in series between the two switching terminals; a control circuit having a first input for receiving a switching signal and a second input for receiving a signal for activating the device, the control circuit being configured to put the switching device into an inactive state or an active state; a driver circuit for applying the switching signal to the gate of the high voltage transistor, the driver circuit being supplied with a first voltage from a first voltage source (VDR+) and with a second voltage from a second voltage source (VDR?), the first and second voltages being respectively higher and lower than the threshold voltage of the high voltage transistor; and at least one programming module associated with the driver circuit, configured to program the incoming current which is to be injected at the gate of the high voltage transistor, and the o

Abstract: A power circuit switching device includes two switching terminals; a high voltage depletion mode transistor and a low voltage enhancement mode transistor arranged in series between the two switching terminals; a control circuit having a first input for receiving a switching signal and a second input for receiving a signal for activating the device, the control circuit being configured to put the switching device into an inactive state or an active state; a driver circuit for applying the switching signal to the gate of the high voltage transistor, the driver circuit being supplied with a first voltage from a first voltage source (VDR+) and with a second voltage from a second voltage source (VDR?), the first and second voltages being respectively higher and lower than the threshold voltage of the high voltage transistor; and at least one programming module associated with the driver circuit, configured to program the incoming current which is to be injected at the gate of the high voltage transistor, and the o

Abstract: An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.

Abstract: An integrated circuit comprises a housing, a plurality of connection pins, a first chip that includes a high-voltage depletion mode transistor, and a second chip that includes a low-voltage enhancement mode transistor. The first chip and second chip each comprise a gate bump contact, a drain bump contact and a source bump contact. The source bump contact of the high-voltage transistor is electrically connected to the drain bump contact of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin that is electrically connected to the source bump contact of the low-voltage transistor.

Abstract: A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and the inside. Inside the package, a bidirectional vertical power transistor is present with a controllable bidirectional current path, through a body of the bidirectional vertical power transistor, between a first current terminal of the bidirectional vertical power transistor connected to the first current pin and a second current terminal of the bidirectional vertical power transistor connected to the second current pin. A control circuit connects the control pin to the body terminal and the control terminal to drive the body and the control terminal, which allows current through the body in a forward direction, from the first current terminal to the second terminal, as a function of the control voltage, and to block current in a reverse direction regardless of the voltage.

Abstract: A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an ON state to a latched-OFF state in which the control component is arranged to configure the switching device to be turned off to decouple the load node from the power supply node. Having transition to the latched-Off state, the control component is further arranged to determine whether a voltage level at the load node exceeds a threshold voltage level, and if it is determined that the voltage level at the load node exceeds the threshold voltage level, transition the power switch module from the latched-OFF state to a current-limited state in which the control component is arranged to control the switching device to limit current-flow there through.

Abstract: Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Abstract: A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

Abstract: Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Abstract: A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an ON state to a latched-OFF state in which the control component is arranged to configure the switching device to be turned off to decouple the load node from the power supply node. Having transition to the latched-Off state, the control component is further arranged to determine whether a voltage level at the load node exceeds a threshold voltage level, and if it is determined that the voltage level at the load node exceeds the threshold voltage level, transition the power switch module from the latched-OFF state to a current-limited state in which the control component is arranged to control the switching device to limit current-flow there through.