Patents by Inventor Lavi Koch
Lavi Koch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056380Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.Type: ApplicationFiled: February 27, 2023Publication date: February 15, 2024Inventors: Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Lavi Koch, Oded Nadir
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Publication number: 20240039689Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.Type: ApplicationFiled: November 27, 2022Publication date: February 1, 2024Inventors: Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman, Lavi Koch
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Patent number: 11637557Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.Type: GrantFiled: February 14, 2022Date of Patent: April 25, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Publication number: 20220173741Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Patent number: 11349780Abstract: A network element includes at least one communication port and a processor. The communication port is configured to communicate with a peer communication port of a peer network element. The processor is configured to support a full-boot mode and a fast-boot mode, to establish, by negotiation with the peer network element, whether the fast-boot mode is supported both for the communication port and for the peer communication port, and, in response to finding that the fast-boot mode is supported both for the communication port and for the peer communication port, to coordinate with the peer network element a boot of the communication port and of the peer communication port, both using the fast-boot mode.Type: GrantFiled: September 3, 2020Date of Patent: May 31, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Sagi Rotem, Zvi Rechtman, Lavi Koch, Roee Shapiro
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Patent number: 11283454Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: GrantFiled: July 6, 2020Date of Patent: March 22, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Publication number: 20220070117Abstract: A network element includes at least one communication port and a processor. The communication port is configured to communicate with a peer communication port of a peer network element. The processor is configured to support a full-boot mode and a fast-boot mode, to establish, by negotiation with the peer network element, whether the fast-boot mode is supported both for the communication port and for the peer communication port, and, in response to finding that the fast-boot mode is supported both for the communication port and for the peer communication port, to coordinate with the peer network element a boot of the communication port and of the peer communication port, both using the fast-boot mode.Type: ApplicationFiled: September 3, 2020Publication date: March 3, 2022Inventors: Sagi Rotem, Zvi Rechtman, Lavi Koch, Roee Shapiro
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Publication number: 20220021393Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: ApplicationFiled: July 6, 2020Publication date: January 20, 2022Inventors: Ran Ravid, Aviv Berg, Lavi Koch, Chen Gaist, Dotan David Levi
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Patent number: 10951545Abstract: Apparatus including a network element including an input-output port, the input-output port including an input data lane and an output data lane, wherein the input data lane is in wired connection with a network data source external to the network element, the output data lane is in wired connection with a network data destination external to the network element, and the network data source is distinct from the network data destination. Related apparatus and methods are also described.Type: GrantFiled: April 15, 2019Date of Patent: March 16, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Barak Gafni, Lavi Koch, Zvi Rechtman
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Publication number: 20210041927Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Inventors: George Elias, Ido Bourstein, Lior Abramovsky, Lavi Koch
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Patent number: 10915154Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.Type: GrantFiled: August 8, 2019Date of Patent: February 9, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: George Elias, Ido Bourstein, Lior Abramovsky, Lavi Koch
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Publication number: 20200328987Abstract: Apparatus including a network element including an input-output port, the input-output port including an input data lane and an output data lane, wherein the input data lane is in wired connection with a network data source external to the network element, the output data lane is in wired connection with a network data destination external to the network element, and the network data source is distinct from the network data destination. Related apparatus and methods are also described.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Barak Gafni, Lavi Koch, Zvi Rechtman
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Patent number: 10778406Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: GrantFiled: November 26, 2018Date of Patent: September 15, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Chen Gaist, Ran Ravid, Aviv Berg, Lavi Koch
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Publication number: 20200169379Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.Type: ApplicationFiled: November 26, 2018Publication date: May 28, 2020Inventors: Chen Gaist, Ran Ravid, Aviv Berg, Lavi Koch
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Patent number: 10503682Abstract: A network adapter includes one or more ports for communicating over a communication network, a bus interface, and logic circuitry. The bus interface is configured to communicate over a bus. The logic circuitry is configured to receive bus configuration request packets from an originator, to control the bus interface to generate one or more bus configuration cycles in response to at least some of the bus configuration request packets, and, in response to the bus configuration cycles, to generate and send bus configuration response packets to the originator of the bus configuration request packets.Type: GrantFiled: December 19, 2018Date of Patent: December 10, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yoni Galezer, Lavi Koch, Tova Bar Asher
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Patent number: 10412673Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.Type: GrantFiled: May 28, 2017Date of Patent: September 10, 2019Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Gil Levy, Liron Mula, Aviv Kfir, Lavi Koch
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Patent number: 10324513Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.Type: GrantFiled: August 27, 2015Date of Patent: June 18, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch, Lavi Koch
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Publication number: 20180343613Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.Type: ApplicationFiled: May 28, 2017Publication date: November 29, 2018Inventors: Gil Levy, Liron Mula, Aviv Kfir, Lavi Koch
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Publication number: 20180199292Abstract: Power consumption is controlled in a fabric of interconnected network switches in which there are queues for data awaiting transmission through the fabric and a plurality of lanes for carrying the data between ports of the switches, A bandwidth manager iteratively determines current queue byte sizes, and assigns respective bandwidths to the switches according to the current queue byte sizes. Responsively to the assigned bandwidths, the bandwidth manager causes a portion of the lanes of the switches to be disabled so as to maintain a power consumption of the fabric below a predefined limit.Type: ApplicationFiled: January 8, 2017Publication date: July 12, 2018Inventors: Liron Mula, Lavi Koch, Gil Levy, Aviv Kfir, Benny Koren
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Publication number: 20160062442Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch, Lavi Koch