Abstract: An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.

Abstract: An integrated circuit and a method for reducing violations of a timing constraint. The integrated circuit comprises a shared resource for providing data and a buffer for storing data. A buffer level monitor is coupled to the buffer, for monitoring a monitored level of data in the buffer. A retrieving circuit is coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint. A filling circuit is coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource.

Abstract: A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.

Abstract: A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.

Abstract: A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.