Abstract: Hot connection and disconnection of an external graphics cable with an information handling system provides automatic selection of an external graphics device or an internal graphics device for presentation of visual information. A graphics state module periodically stores visual information, such as display objects for recreating a display frame, and monitors an external graphics device port, such as a PCI Express port, to detect a change in connection state at the external graphics port. Upon detection of a connection or disconnection at the external graphics port, the graphics state module attempts to initiate graphics devices in a predetermined order and provides the stored visual information for presentation at successfully initiated graphics devices according to the predetermined order.

Abstract: A self calibrating video circuit comprises a first and second digital-to-analog converter generating first and second output signals, and a calibration circuit coupled with the first and second digital-to-analog converters for calibrating the first digital-to-analog converter output signal to the output signal of the second digital-to-analog converter.

Abstract: A self-calibrating video circuit comprises a first and second digital-to-analog converter generating first and second output signals, and a calibration circuit coupled with the first and second digital-to-analog converters for calibrating the first digital-to-analog converter output signal to the output signal of the second digital-to-analog converter.

Abstract: An improved cascode current switch circuit particularly adapted for use in a data system or the like. The circuit provides a binary output, or an inhibit output under the control of a select/deselect input. The circuit includes interconnected upper and lower current switch circuits and is characterized by power reduction circuit means interconnecting the upper and lower current switches.

Abstract: A sense amplifier circuit for use with a directory memory chip in which the output of a corresponding memory cell is sensed and output signals representing the sensed bit state are provided to first and second output ports. The signal provided to the first output port can be selectively inhibited, although, when not inhibited, the signals applied to the first and second output ports occur simultaneously. The inhibiting function may be performed by a dual-emitter circuit and switchable current source in one of two sense amplifiers.