Abstract: A cask liner includes a hollow cylinder comprising a boron-containing composition. The hollow cylinder has no longitudinal joints. The hollow cylinder may be formed as a single unit by isostatic pressing, for example by hot isostatic pressing (HIP) of a blend of a boron-containing powder and an aluminum or aluminum alloy powder which is blended by mechanical alloying. Casked nuclear fuel includes a nuclear fuel rod comprising uranium, which is disposed in or extends through the hollow cylinder of the cask liner.

Abstract: A surface mountable laser driver circuit package is configured to mount on a host printed circuit board (PCB). A surface mount circuit package includes a lead-frame. A plurality of laser driver circuit components is mounted on and in electrical communication with the lead-frame of the surface mount circuit package. A dielectric layer is located between the lead-frame and the host PCB and includes portals through the dielectric layer each arranged to accommodate an electrical connection between the lead-frame and the host PCB. The lead-frame and the dielectric layer are arranged such that a first lead-frame portion and a first dielectric layer portal align with a first end of a host PCB trace configured to provide a current return path for the surface mount laser driver, and a second lead-frame portion and a second dielectric layer portal align with a second end of the host PCB trace.

Abstract: A semiconductor package is manufactured by physically attaching a side emitting laser diode to a floor portion of a recessed flat no-leads (FNL) package having a wall extending from and surrounding a perimeter of a recessed floor portion. The attached side emitting laser diode is oriented to direct a laser beam toward an opposing portion of the wall. The FNL package is singulated into a first piece and a second piece along a singulation plane through the FNL package wall and floor portion between the side emitting laser diode and the opposing portion of the wall. After singulation the opposing portion of the wall is in the second piece and the side emitting laser diode is in the first piece.

Abstract: A semiconductor package is manufactured by physically attaching a side emitting laser diode to a floor portion of a recessed flat no-leads (FNL) package having a wall extending from and surrounding a perimeter of a recessed floor portion. The attached side emitting laser diode is oriented to direct a laser beam toward an opposing portion of the wall. The FNL package is singulated into a first piece and a second piece along a singulation plane through the FNL package wall and floor portion between the side emitting laser diode and the opposing portion of the wall. After singulation the opposing portion of the wall is in the second piece and the side emitting laser diode is in the first piece.

Abstract: A low inductance electrical switching circuit arrangement, includes a two sided substrate with a plurality of through-substrate electrical vias. A capacitor is arranged on the substrate first side above a first via, and an electrical sink is arranged on the first side above a second via. A switching component configured to produce a plurality of current pulses is arranged on the substrate second side below the first and second via.

Abstract: A surface mountable laser driver circuit package is configured to mount on a host printed circuit board (PCB). A surface mount circuit package includes a lead-frame. A plurality of laser driver circuit components is mounted on and in electrical communication with the lead-frame of the surface mount circuit package. A dielectric layer is located between the lead-frame and the host PCB and includes portals through the dielectric layer each arranged to accommodate an electrical connection between the lead-frame and the host PCB. The lead-frame and the dielectric layer are arranged such that a first lead-frame portion and a first dielectric layer portal align with a first end of a host PCB trace configured to provide a current return path for the surface mount laser driver, and a second lead-frame portion and a second dielectric layer portal align with a second end of the host PCB trace.

Abstract: A chip slapper is presented, having a substrate, a conductive layer disposed above the substrate face, and an intermediate layer disposed between the substrate face and the conductive layer. The conductive layer and intermediate layer form a first land and a second land atop the substrate face, with a bridge formed of the intermediate layer spanning between the first land and the second land. A first adhesion portion is attached to the first land, and a second adhesion portion is attached to the second land, wherein at least a portion of the bridge is not overlaid by the first adhesion portion or the second adhesion portion.

Abstract: A chip slapper is presented, having a substrate, a conductive layer disposed above the substrate face, and an intermediate layer disposed between the substrate face and the conductive layer. The conductive layer and intermediate layer form a first land and a second land atop the substrate face, with a bridge formed of the intermediate layer spanning between the first land and the second land. A first adhesion portion is attached to the first land, and a second adhesion portion is attached to the second land, wherein at least a portion of the bridge is not overlaid by the first adhesion portion or the second adhesion portion.

Abstract: A method of reducing variation in optical power levels across a group of light emitting diodes includes testing each respective one of the light emitting diodes to determine an optical power level produced by that light emitting diode when connected to an electrical power source. During testing, the electrical power source delivers a substantially identical amount of electrical current to each respective one of the light emitting diodes. The optical power levels from the test all fall within a first range of values. The method includes connecting an electrical resistance in parallel with at least some of the light emitting diodes to reduce an amount of optical power produced by those light emitting diodes. After the electrical resistances are connected, all of the optical power levels produced by the light emitting diodes fall within a second range that is narrower than the first range.

Abstract: A method of reducing variation in optical power levels across a group of light emitting diodes includes testing each respective one of the light emitting diodes to determine an optical power level produced by that light emitting diode when connected to an electrical power source. During testing, the electrical power source delivers a substantially identical amount of electrical current to each respective one of the light emitting diodes. The optical power levels from the test all fall within a first range of values. The method includes connecting an electrical resistance in parallel with at least some of the light emitting diodes to reduce an amount of optical power produced by those light emitting diodes. After the electrical resistances are connected, all of the optical power levels produced by the light emitting diodes fall within a second range that is narrower than the first range.

Abstract: High quantum efficiency photodiode device having a pair of photodiodes with light receiving surfaces in parallel spaced relation in a closed cavity. Light is admitted to the cavity through an aperture in such manner that it impinges obliquely upon the light receiving surfaces and is reflected back and forth between the diodes until absorbed. A mirror positioned at the end of the diodes opposite the aperture reflects impinging thereon back to the photodiodes.

Abstract: Photodiode structure and method of manufacturing the same, wherein the photodiode has a combination of very high shunt resistance and exceptionally low capacitance with only a slight loss in sensitivity. The diode junction is formed by a narrow line, and the geometry of the device can take many forms. The device has a typical shunt resistance of 150 megohms and a typical capacitance of 80 picofarads for an equivalent photosensitive area of 1 cm.sup.2, which cannot be achieved by current standard technology.