Abstract: Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.

Abstract: An apparatus and method for providing home evolved node-B (H(e)NB) integrity verification and validation using autonomous validation and semi-autonomous validation is disclosed herein.

Abstract: Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.

Abstract: A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.

Abstract: Embodiments include systems and methods for securely accessing data in the context of a data transaction. A system may include a memory block, within which a memory partition may be allocated to the data transaction. The memory partition includes a data storage block and at least one binding register. The system also includes platform entities and an access control block, which determines whether a particular platform entity may access data within the data storage block, and whether a particular platform entity may write binding information into a binding register. Access also may be granted or denied based on the current state of a state machine associated with the data transaction. The system also includes a cipher/binding function adapted to encrypt the data, using the binding information, for storage on an unsecured memory device, and to decrypting encrypted data, using the binding information, which is retrieved from the unsecured memory device.

Abstract: Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.

Abstract: A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.

Abstract: A system-on-a-chip and method for securely transferring data can include a trusted master; a first trusted slave; an untrusted component; and a common bus coupling the trusted master, the first trusted slave, and the untrusted component, In response to an initiation by a host, the trusted master provides a first access request to request a first data transfer with the first trusted slave, and wherein the trusted master does not perform the first data transfer until authentication of the first trusted slave.

Abstract: A secure processing system is provided with increased flexibility to secure different categories of data from different entities (e.g., different users or stakeholders) both from external access and from other entities that use the same system. In one embodiment, the secure processing system includes a host processor and a secure memory system which provides for the storage of sensitive data in encrypted form in a storage medium external to the secure processing system. In accordance with the embodiments of the invention, a key generator is provided that uses a base encryption key and a plurality of key modifiers to create a plurality of derivative keys. The derivative keys are used by encryption logic circuitry within the secure memory system for encrypting and decrypting sensitive information. The derivative keys created by the key generator are used to secure different categories of data from different entities.

Abstract: A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.