Patents by Inventor Lawrence S. Melvin, III
Lawrence S. Melvin, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7721246Abstract: One embodiment of the present invention determines the effect of placing an assist feature at a location in a layout. During operation, the system receives a first value which was pre-computed by convolving a model with a layout at an evaluation point, wherein the model models semiconductor manufacturing processes. Next, the system determines a second value by convolving the model with an assist feature, which is assumed to be located at a first location which is in proximity to the evaluation point. The system then determines the effect of placing an assist feature using the first value and the second value. An embodiment of the present invention can be used to determine a substantially optimal location for placing an assist feature in a layout.Type: GrantFiled: October 19, 2006Date of Patent: May 18, 2010Assignee: Synopsys, Inc.Inventors: Jianliang Li, Qiliang Yan, Lawrence S. Melvin, III, Levi D. Barnes, Abani M. Biswas, Alakananda A. Biswas, legal representative
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Patent number: 7707539Abstract: An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then modify the mask layout in proximity to the set of corners to obtain a modified mask layout. Alternatively, the system may determine a set of mask layers. Next, the system may determine an improved process model by calibrating the uncalibrated process model using the modified mask layout and/or the set of mask layers, and the process data.Type: GrantFiled: September 28, 2007Date of Patent: April 27, 2010Assignee: Synopsys, Inc.Inventors: Jensheng Huang, Chun-chieh Kuo, Lawrence S. Melvin, III
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Publication number: 20100092880Abstract: One embodiment of the present invention provides a method to facilitate using a synchrotron as a source in an extreme ultraviolet lithography (EUVL) system, wherein the synchrotron's energy decreases over time. The EUVL system can includes a stepper which uses a step-and-repeat process or a step-and-scan process to transfer patterns from a reticle onto a wafer. The wafer is desired to be exposed to a substantially constant dose. During operation, the system can measure a synchrotron current, and adjust the stepper's exposure duration or the stepper's scan speed based on the synchrotron current so that the wafer is exposed to the substantially constant dose. Note that using the synchrotron current to control the stepper can enable the EUVL system to expose the wafer to the substantially constant dose without using additional equipment to monitor the source's energy.Type: ApplicationFiled: October 14, 2008Publication date: April 15, 2010Applicant: SYNOPSYS, INC.Inventor: Lawrence S. Melvin, III
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Publication number: 20100095264Abstract: One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a second layout, wherein the wafer includes topography variations that were caused by resist features that were created when the wafer was exposed to a first layout. The process model can include a first term and a second term, wherein the first term is convolved with a sum of the first layout and the second layout, and wherein the second term is convolved with the second layout.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: SYNOPSYS, INC.Inventors: Jensheng Huang, Lawrence S. Melvin, III
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Publication number: 20100086196Abstract: One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's optical system under different focus conditions. Next, the system can determine a location in proximity to the iso-focal pattern where the aerial-image-intensity values are substantially insensitive to focus variations. The system can then use the location and the associated aerial-image-intensity values to determine an optical threshold and a resist bias. The optical threshold and the resist bias can then be used for modeling the photolithography process.Type: ApplicationFiled: October 2, 2008Publication date: April 8, 2010Applicant: SYNOPSYS, INC.Inventors: Jianliang Li, Lawrence S. Melvin III, Qiliang Yan
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Publication number: 20090292508Abstract: One embodiment of the present invention provides techniques and systems for modeling long-range extreme ultraviolet lithography (EUVL) flare. During operation, the system may receive an evaluation point in a layout. Next, the system may receive an EUVL model which includes kernels that are discretized at different sampling rates, and which have different sized ambits. Specifically, a kernel that is discretized using a low sampling rate may have a longer range than a kernel that is discretized using a high sampling rate. The system may then convolve the kernels with the layout at the evaluation point over their respective ambits. Next, the system may use the convolution results to determine an indicator value. The indicator value can be used for a number of applications, e.g., to predict pattern shapes that are expected to print on a wafer, to perform optical proximity correction, or to identify manufacturing problem areas in the layout.Type: ApplicationFiled: May 23, 2008Publication date: November 26, 2009Applicant: SYNOPSYS, INC.Inventors: Lawrence S. Melvin, III, Brian S. Ward, Kunal N. Taravade
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Publication number: 20090288047Abstract: One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicant: SYNOPSYS, INC.Inventors: Zong Wu Tang, Daniel N. Zhang, Juhwan Kim, Hua Song, Weiping Fang, Lawrence S. Melvin, III
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Patent number: 7584450Abstract: One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems.Type: GrantFiled: December 12, 2006Date of Patent: September 1, 2009Assignee: Synopsys, Inc.Inventors: Zong Wu Tang, Daniel N. Zhang, Juhwan Kim, Hua Song, Weiping Fang, Lawrence S. Melvin, III
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Publication number: 20090089736Abstract: An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then modify the mask layout in proximity to the set of corners to obtain a modified mask layout. Alternatively, the system may determine a set of mask layers. Next, the system may determine an improved process model by calibrating the uncalibrated process model using the modified mask layout and/or the set of mask layers, and the process data.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: Synopsys, Inc.Inventors: Jensheng Huang, Chun-chieh Kuo, Lawrence S. Melvin, III
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Patent number: 7509621Abstract: One embodiment of the present invention provides a system that determines a location in a layout to place an assist feature. During operation, the system receives a layout of an integrated circuit. Next, the system selects an evaluation point in the layout. The system then chooses a candidate location in the layout for placing an assist feature. Next, the system determines the final location in the layout to place an assist feature by, iteratively, (a) selecting perturbation locations for placing representative assist features in the proximity of the candidate location, (b) computing aerial-images using an image intensity model, the layout, and by placing representative assist features at the candidate location and the perturbation locations, (c) calculating image-gradient magnitudes at the evaluation point based on the aerial-images, and (d) updating the candidate location for the assist feature based on the image-gradient magnitudes.Type: GrantFiled: January 3, 2005Date of Patent: March 24, 2009Assignee: Synopsys, Inc.Inventor: Lawrence S. Melvin, III
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Patent number: 7509624Abstract: One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a layout. The system then selects a segment in the layout. Next, the system determines a target location in the proximity of the segment where the value of a process-sensitivity model is within a desired range of values. The system then modifies the layout so that the segment is located at the target location. The layout modification can cause the pattern which is associated with the segment to exhibit isofocal behavior, which can improve manufacturing robustness.Type: GrantFiled: May 24, 2006Date of Patent: March 24, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Ebo K.G. Croffie
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Patent number: 7494751Abstract: One embodiment of the present invention provides a system that improves the depth of focus during an optical lithography process. During operation, the system receives a mask layout. The system then selects an edge in the mask layout. Next, the system adds a notch to the edge to improve the depth of focus by helping to maintain a critical dimension associated with the edge as the optical lithography process drifts out of focus. Note that adding a notch to the edge adds a high spatial-frequency component to the mask layout. This high spatial-frequency component degrades as the optical lithography process drifts out of focus. This degradation causes the mask layout to allow more light into the pattern, which helps maintain the critical dimension, thereby improving depth of focus.Type: GrantFiled: January 27, 2005Date of Patent: February 24, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, James P. Shiely
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Patent number: 7496880Abstract: One embodiment of the present invention provides a system that assesses the quality of a process model. During operation, the system receives a mask layout and additionally receives a process model that models the effects of one or more semiconductor manufacturing processes on the mask layout. Next, the system computes a gradient of the process model with respect to a process model parameter. The system then computes a quality indicator at an evaluation point in the mask layout using the gradient of the process model and the mask layout. Next, the system assesses the quality of the process model using the quality indicator. In one embodiment, the system assesses the quality of the process model by comparing the quality indicator with a threshold.Type: GrantFiled: October 3, 2005Date of Patent: February 24, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Qiliang Yan
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Patent number: 7491479Abstract: One embodiment of the present invention provides a system that accurately determines a critical dimension of a feature in a layout by compensating for the effects of topography variation on the performance of an optical lithography process. During operation, the system first receives a layout. Next, the system computes and aerial-image intensity at an evaluation point in the layout using and optical lithography model that models the optical lithography process. Note that the aerial-image intensity is typically compared with a constant intensity threshold to determine a critical dimension of a feature in the layout. The system then computes an intensity threshold based on features in the proximity of the evaluation point, which compensates for the effects of topography variations on the performance of the optical lithography process.Type: GrantFiled: October 7, 2005Date of Patent: February 17, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Jensheng Huang
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Patent number: 7475382Abstract: One embodiment of the present invention provides a system that determines the locations and dimensions of one or more assist features in an uncorrected or corrected mask layout. During operation, the system receives a mask layout. The system then creates a set of candidate assist feature configurations, which specify locations and sizes for one or more assist features in the mask layout. Next, the system determines an improved assist feature configuration using the set of candidate assist feature configurations and a process-sensitivity model which can be represented by a multidimensional function that captures process-sensitivity information. Note that placing assist features in the mask layout based on the improved assist feature configuration improves the manufacturability of the mask layout. Moreover, using the process-sensitivity model to determine the improved assist feature configuration reduces the computational time required to determine the improved assist feature configuration in the mask layout.Type: GrantFiled: April 19, 2005Date of Patent: January 6, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Benjamin D. Painter
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Patent number: 7454739Abstract: One embodiment of the present invention provides a system that determines an accurate process model. During operation, the system receives process data. Next, the system receives an optical model which models an optical system of a photolithography process. The system then determines a stack model using the optical model, wherein the stack model models the effects of the photolithography process on the stack layers. Finally, the system determines a process model using the optical model, the stack model, and the process data.Type: GrantFiled: May 31, 2006Date of Patent: November 18, 2008Assignee: Synopsys, Inc.Inventors: Jensheng Huang, Chun-Chieh Kuo, Lawrence S. Melvin, III
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Patent number: 7451068Abstract: One embodiment of the invention provides a system that dissects edges of a layout of an integrated circuit to produce a segmentation of the layout for a subsequent optical proximity correction (OPC) operation. In order to perform the dissection, the system first performs a model-based simulation on the layout to generate intensity gradients along edges of features in the layout. Next, the system generates a segmentation for edges in the layout based upon the intensity gradients. This segmentation is used during a subsequent optical proximity correction (OPC) process to generate corrections for the layout so that the layout prints more accurately on a semiconductor chip.Type: GrantFiled: October 10, 2003Date of Patent: November 11, 2008Assignee: Synopsys, Inc.Inventor: Lawrence S. Melvin, III
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Patent number: 7421678Abstract: One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial assist feature placement. An assist feature perturbation typically comprises a few simple polygons. The system then determines perturbation values at evaluation points in the layout using the assist feature perturbations and an analytical model. If a process-sensitivity model is used, the perturbation value at an evaluation point is associated with the change in the through-process window at that point in the layout. Next, the system determines a change in the value of an objective function using the perturbation values. The objective function can be indicative of the overall manufacturability of the layout. The system then determines an assist feature placement using the change in the value of the objective function.Type: GrantFiled: May 12, 2006Date of Patent: September 2, 2008Assignee: Synopsys, Inc.Inventors: Levi D. Barnes, Lawrence S. Melvin, III, Benjamin D. Painter
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Patent number: 7320119Abstract: One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.Type: GrantFiled: May 6, 2005Date of Patent: January 15, 2008Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, James P. Shiely, Qiliang Yan, Benjamin D. Painter
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Patent number: 7315999Abstract: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems due to a missing or an improperly placed assist feature. During operation, the system receives an uncorrected or corrected mask layout. The system then dissects the mask layout into segments. Next, the system identifies a problem area associated with a segment using a process-sensitivity model which can be represented by a multidimensional function that captures process-sensitivity information. Note that identifying the problem area allows a new assist feature to be added or an existing assist feature to be adjusted, thereby improving the wafer manufacturability. Moreover, using the process-sensitivity model reduces the computational time required to identify the problem area.Type: GrantFiled: April 19, 2005Date of Patent: January 1, 2008Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Benjamin D. Painter