Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Abstract: Methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a fluorine-free tungsten precursor and hydrogen in cycles of temporally separated pulses, are provided. Some methods involve depositing fluorine-free tungsten by sequential CVD without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface. Methods also include depositing a tungsten layer using a reducing agent and fluorine-free tungsten-containing precursor and depositing bulk tungsten in sequential CVD cycles of alternating pulses of hydrogen and a tungsten-containing precursor.

Abstract: Provided herein are methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a chlorine-containing tungsten precursor and hydrogen in cycles of temporally separated pulses, without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: Aspects of the methods and apparatus described herein relate to deposition of tungsten nucleation layers and other tungsten-containing films. Various embodiments of the methods involve exposing a substrate to alternating pulses of a tungsten precursor and a reducing agent at low chamber pressure to thereby deposit a tungsten-containing layer on the surface of the substrate. According to various embodiments, chamber pressure may be maintained at or below 10 Torr. In some embodiments, chamber pressure may be maintained at or below 7 Torr, or even lower, such as at or below 5 Torr. The methods may be implemented with a fluorine-containing tungsten precursor, but result in very low or undetectable amounts of fluorine in the deposited layer.

Abstract: Provided herein are methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a chlorine-containing tungsten precursor and hydrogen in cycles of temporally separated pulses, without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface.

Abstract: Provided herein are methods of depositing bulk tungsten by sequential CVD pulses, such as by alternately pulsing tungsten hexafluoride and hydrogen gas in cycles of temporally separated pulses. Some methods include depositing a tungsten nucleation layer at low pressure followed by deposition of bulk tungsten by sequential CVD to form low stress tungsten films with low fluorine content. Methods described herein may also be performed in combination with non-sequential CVD deposition and fluorine-free tungsten deposition techniques.

Abstract: Aspects of the methods and apparatus described herein relate to deposition of tungsten nucleation layers and other tungsten-containing films. Various embodiments of the methods involve exposing a substrate to alternating pulses of a tungsten precursor and a reducing agent at low chamber pressure to thereby deposit a tungsten-containing layer on the surface of the substrate. According to various embodiments, chamber pressure may be maintained at or below 10 Torr. In some embodiments, chamber pressure may be maintained at or below 7 Torr, or even lower, such as at or below 5 Torr. The methods may be implemented with a fluorine-containing tungsten precursor, but result in very low or undetectable amounts of fluorine in the deposited layer.

Abstract: Provided herein are methods of depositing bulk tungsten by sequential CVD pulses, such as by alternately pulsing tungsten hexafluoride and hydrogen gas in cycles of temporally separated pulses. Some methods include depositing a tungsten nucleation layer at low pressure followed by deposition of bulk tungsten by sequential CVD to form low stress tungsten films with low fluorine content. Methods described herein may also be performed in combination with non-sequential CVD deposition and fluorine-free tungsten deposition techniques.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).