Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: Non-ideal downstream loading of a differential driver in a single ended circuit driving a communications laser—e.g., Electro absorption Modulated Laser (EML)—may be compensated by deploying a second matching network at the non-functional (terminated) driver output node. Certain embodiments may further compensate for distortion arising from circuit non-ideality, by introducing a laser replica downstream of the second matching network to mimic electrical properties of the laser. Embodiments may sufficiently compensate for downstream circuit non-ideality to allow replacing the bulky choke inductor of a bias tee, with a resistor. Substituting a resistor for a more complex inductor structure can simplify design and fabrication of the single-ended driver circuit, and also reduce footprint by eliminating area formerly occupied by the choke inductor.

Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.

Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: An active network system for a host device with a host processor, comprises a wireless port including a first physical layer/medium access control (PHY/MAC) device. A first wired port includes a second PHY/MAC device. A secondary processor communicates with the wireless port, the first wired port and the host processor. The secondary processor, the wireless port and the first wired port support network functionality when the host processor is an inactive mode. The network functionality includes at least one of access point functionality, router functionality, repeater functionality, point-to-point functionality and point-to-multipoint functionality.

Abstract: The present system and method manage a rechargeable battery comprising two or more battery cells or series stacks of cells. The system includes a set of switches, each of which connects a cell or stack of cells between positive and negative nodes when actuated, or connects one cell in a stack of cells to another cell in the stack when actuated, such that when all the switches in a given stack are actuated, it is connected between the positive and negative nodes. An electrical load is directly connected to the positive and negative nodes. A controller determines the state of each cell or stack of cells by measuring and/or calculating one or more predetermined characteristics, and selectively actuates the switches based on the states of the cells or stacks of cells so as to enhance the life of the battery.

Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N?1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N?1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

Abstract: A voltage regulator for a plurality of radio frequency subcircuits of a radio frequency circuit. A first transistor configured to receive, based on a comparison between a reference voltage signal and a feedback signal, a bias signal corresponding to a desired regulated voltage for the plurality of radio frequency subcircuits, output the bias signal, and generate the feedback signal according to the bias signal as output from the first transistor. A second transistor configured to receive the bias signal as output from the first transistor and provide, based on the bias signal, the desired regulated voltage to a respective first one of the plurality of radio frequency subcircuits. A third transistor is configured to receive the bias signal as output from the first transistor and provide, based on the bias signal, the desired regulated voltage to a respective second one of the plurality of radio frequency subcircuits.

Abstract: A system including a component of a transceiver, a comparator, a counter, and a calibration circuit. The component receives an input signal comprising packets and based on the input signal, generates output signals to transmit the packets. The comparator compares the output signals to generate a comparison signal. The counter counts cycles of a clock signal to provide a count value. The control device, based on the comparison signal, transitions the counter between incrementing the count value and decrementing the count value. The calibration circuit operates in first and second calibration modes; during the first calibration mode, calibrates the component until the counter transitions a predetermined number of times between incrementing the count value and decrementing the count value; and during the second calibration mode, calibrates the component until (i) the counter transitions between incrementing and decrementing the count value, or (ii) counts a predetermined number of cycles.

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: Different scan modes are provided for Bluetooth devices. In at least some embodiments, a narrowband scanning mode looks for signal energy on individual transmission frequencies at a time. By looking for signal energy rather than decoding transmitted packets, at least some of the components in a Bluetooth device can remain in an idle or rest state. A midband scanning mode looks for signal energy across multiple different frequencies at a time. Again, by looking for signal energy across multiple different frequencies rather than decoding transmitted packets, at least some of the components in a Bluetooth device can remain in an idle or rest state. A wideband scanning mode looks for signal energies across all relevant frequencies at a time. At least some embodiments enable a Bluetooth device to switch between scanning modes.

Abstract: A network interface includes a network interface controller and a plurality of communication paths between a host and a plurality of different networks. Each of the plurality of communication paths includes a media access controller and a physical layer device. The media access controller is configured to use a same media access controller address for communicating with a respective one of the plurality of different networks. The physical layer device configured to determine at least one of an availability of the respective one of the plurality of different networks and a performance condition of the respective one of the plurality of different networks. The network interface controller is configured to receive, from the host, a selection of one of the plurality of different networks and activate one of the plurality of communications paths based on the selection.

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: Different scan modes are provided for Bluetooth devices. In at least some embodiments, a narrowband scanning mode looks for signal energy on individual transmission frequencies at a time. By looking for signal energy rather than decoding transmitted packets, at least some of the components in a Bluetooth device can remain in an idle or rest state. A midband scanning mode looks for signal energy across multiple different frequencies at a time. Again, by looking for signal energy across multiple different frequencies rather than decoding transmitted packets, at least some of the components in a Bluetooth device can remain in an idle or rest state. A wideband scanning mode looks for signal energies across all relevant frequencies at a time. At least some embodiments enable a Bluetooth device to switch between scanning modes.

Abstract: A radio frequency transceiver for a wireless communications device transceiver comprising a plurality of subcircuits, a first regulator circuit, and a plurality of second regulator circuits. Each subcircuit is configured to perform an operation of the radio frequency transceiver in accordance with a corresponding regulated voltage. A first regulator circuit is configured to provide a bias signal based on a reference signal and a feedback signal indicative of the bias signal. The bias signal corresponds to a desired regulated voltage for the plurality of subcircuits. A plurality of second regulator circuits corresponding to respective ones of the plurality of subcircuits are each configured to provide the regulated voltage to the respective one of the plurality of subcircuits.