Patents by Inventor Lay Hong LEE

Lay Hong LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9165795
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 20, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Lay Hong Lee
  • Publication number: 20140061895
    Abstract: A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicant: Spansion LLC
    Inventors: Yin Lye FOONG, Cheng Sim Kee, Lay Hong Lee, Mohamed Suhaizal Bin Abu-Hassan
  • Patent number: 8586413
    Abstract: A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: November 19, 2013
    Assignee: Spansion LLC
    Inventors: Yin Lye Foong, Cheng Sim Kee, Lay Hong Lee, Mohamed Suhaizal Bin Abu-Hassan
  • Publication number: 20120146213
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Inventors: Gin Ghee TAN, Lai Beng TEOH, Lay Hong LEE