Patents by Inventor Lay-Lay Chua
Lay-Lay Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8105745Abstract: There is provided a class of crosslinking compound, said compound comprising (i) one or more fluorinated aromatic group; and (ii) one or more ionizable group, wherein the crosslinking compound is soluble in at least one polar solvent. Methods of preparing the crosslinking compounds are also disclosed. There is further provided devices obtainable from the methods of preparing the crosslinking compounds.Type: GrantFiled: July 4, 2006Date of Patent: January 31, 2012Assignee: National University of SingaporeInventors: Peter Kian-Hoon Ho, Lay-Lay Chua, Siong-Hee Khong, Sankaran Sivaramakrishnan, Perq-Jon Chia
-
Publication number: 20110089406Abstract: This invention relates to a supported polymer heterostructure and methods of manufacture. The heterostructure is suitable for use in a range of applications which require semiconductor devices, including photovoltaic devices and light-emitting diodes.Type: ApplicationFiled: November 28, 2008Publication date: April 21, 2011Inventors: Peter Ho, Perq-Jon Chia, Lay-Lay Chua, Rui-Qi Png, Richard Henry Friend
-
Publication number: 20110052813Abstract: A functionalised graphene oxide and a method of making a functionalised graphene oxide comprising: (i) oxidizing graphite to form graphite oxide wherein the graphene sheets which make up the graphite independently of each other have a basal plane fraction of carbon atoms in the sp2-hybridised state between 0.1 and 0.9, wherein the remainder fraction comprises sp3-hybridised carbon atoms which are bonded to oxygen groups selected from hydroxyl and/or epoxy and/or carboxylic acid; and (ii) exfoliating and in-situ functionalizing the graphite oxide surface with one or more functional groups such that functionalisation of the surface is effected at a concentration greater than one functional group per 100 carbon atoms and less than one functional group per six carbon atoms. The functionalised graphene oxide is dispersible at high concentrations in appropriate solvents without aggregating or precipitating over extended periods at room temperature.Type: ApplicationFiled: January 3, 2009Publication date: March 3, 2011Inventors: Peter Ho, Lay-Lay Chua, Shuai Wang, Perq-Jon Chia, Ghim Siong Goh
-
Patent number: 7884355Abstract: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.Type: GrantFiled: May 12, 2004Date of Patent: February 8, 2011Assignee: Cambridge Enterprise LtdInventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Henning Sirringhaus, Richard Henry Friend
-
Patent number: 7718549Abstract: A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric lType: GrantFiled: August 11, 2004Date of Patent: May 18, 2010Assignee: Cambridge University Technical Services LimitedInventors: Lay-lay Chua, Peter Kian-Hoon Ho, Henning Sirringhaus, Richard Henry Friend
-
Patent number: 7638793Abstract: An n-channel or ambipolar field-effect transistor including an organic semiconductive layer having an electron affinity EAsemicond; and an organic gate dielectric layer forming an interface with the semiconductive layer; characterized in that the bulk concentration of trapping groups in the gate dielectric layer is less than 1018 cm?3, where a trapping group is a group having (i) an electron affinity EAX greater than or equal to EAsemicond and/or (ii) a reactive electron affinity EArxn greater than or equal to (EAsemicond.?2 eV).Type: GrantFiled: January 17, 2005Date of Patent: December 29, 2009Assignee: Cambridge Enterprise LtdInventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Richard Henry Friend
-
Patent number: 7595249Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: GrantFiled: September 29, 2008Date of Patent: September 29, 2009Assignee: Alcatel-Lucent USA Inc.Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
-
Publication number: 20090029536Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: ApplicationFiled: September 29, 2008Publication date: January 29, 2009Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
-
Publication number: 20090004402Abstract: There is provided a class of crosslinking compound, said compound comprising (i) one or more fluorinated aromatic group; and (ii) one or more ionisable group, wherein the crosslinking compound is soluble in at least one polar solvent. Methods of preparing the crosslinking compounds are also disclosed. There is further provided devices obtainable from the methods of preparing the crosslinking compounds.Type: ApplicationFiled: July 4, 2006Publication date: January 1, 2009Inventors: Peter Kian-Hoon Ho, Lay-Lay Chua, Siong-Hee Khong, Sankaran Sivaramakrishnan, Perq-Jon Chia
-
Publication number: 20080283825Abstract: A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.Type: ApplicationFiled: April 5, 2005Publication date: November 20, 2008Inventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Richard Henry Friend
-
Publication number: 20080265414Abstract: The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm?1.Type: ApplicationFiled: July 3, 2006Publication date: October 30, 2008Applicant: National University of SingaporeInventors: Peter Kian-Hoon Ho, Lay-Lay Chua, Sankaran Sivaramakrishnan, Perq-Jon Chia
-
Publication number: 20070295955Abstract: An n-channel or ambipolar field-effect transistor including an organic semiconductive layer having an electron affinity EAsemicond; and an organic gate dielectric layer forming an interface with the semiconductive layer; characterised in that the bulk concentration of trapping groups in the gate dielectric layer is less than 1018cm?3, where a trapping group is a group having (i) an electron affinity EAX greater than or equal to EAsemicondand/or (ii) a reactive electron affinity EArxngreater than or equal to (EAsemicond. ?2eV).Type: ApplicationFiled: January 17, 2005Publication date: December 27, 2007Inventors: Lay-Lay Chua, Peter Ho, Richard Friend
-
Publication number: 20070278478Abstract: An ambipolar, light-emitting transistor comprising an organic semiconductive layer in contact with an electron injecting electrode and a hole injecting electrode separated by a distance L defining the channel length of the transistor, in which the zone of the organic semiconductive layer from which the light is emitted is located more than L/10 away from both the electron as well as the hole injecting electrode.Type: ApplicationFiled: January 17, 2005Publication date: December 6, 2007Inventors: Jana Zaumseil, Henning Sirringhaus, Lay-Lay Chua, Peter Ho, Richard Friend
-
Publication number: 20070172978Abstract: A method of forming a polymer device including the steps of: (i) depositing on a substrate a solution comprising a polymer or oligomer and a crosslinking moiety, to form a layer; (ii) curing the layer formed in step (i) under conditions to form an insoluble crosslinked polymer, characterized in that the crosslinking moiety is present in step (i) in an amount in the range of from 0.05 to 5 mol % based on the total number of moles of repeat units of the polymer or oligomer and the crosslinking moiety in the solution.Type: ApplicationFiled: May 12, 2004Publication date: July 26, 2007Applicant: CAMBRIDGE UNIVERSITY TECHNICAL SERVICE LIMITEDInventors: Lay-Lay Chua, Peter Ho, Richard Friend
-
Publication number: 20070071881Abstract: A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric layeType: ApplicationFiled: August 11, 2004Publication date: March 29, 2007Inventors: Lay-lay Chua, Peter Ho, Henning Sirringhaus, Richard Friend
-
Publication number: 20060284166Abstract: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.Type: ApplicationFiled: May 12, 2004Publication date: December 21, 2006Inventors: Lay-Lay Chua, Peter Ho, Henning Sirringhaus, Richard Friend
-
Publication number: 20050255692Abstract: The present invention provides a method for adhering dielectric layers to metals, in particular inert metals, using an adhesive layer comprising silicon-rich silicon nitride. Good adhesion is achieved at temperatures of less than 300° C., thereby facilitating the fabrication of semiconductor structures containing II-VI and III-V semiconductors.Type: ApplicationFiled: July 19, 2005Publication date: November 17, 2005Applicant: Lucent Technologies Inc.Inventors: Yang Yang, Chun-Ting Liu, Rose Kopf, Chen-Jung Chen, Lay-Lay Chua
-
Publication number: 20050230784Abstract: The present invention provides a method for adhering dielectric layers to metals, in particular inert metals, using an adhesive layer comprising silicon-rich silicon nitride. Good adhesion is achieved at temperatures of less than 300° C., thereby facilitating the fabrication of semiconductor structures containing II-VI and III-V semiconductors.Type: ApplicationFiled: January 14, 2003Publication date: October 20, 2005Applicant: Lucent Technologies Inc.Inventors: Yang Yang, Chun-Ting Liu, Rose Kopf, Chen-Jung Chen, Lay-Lay Chua
-
Publication number: 20050156195Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: ApplicationFiled: March 14, 2005Publication date: July 21, 2005Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Houtsma, Rose Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
-
Patent number: 6911716Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: GrantFiled: September 13, 2002Date of Patent: June 28, 2005Assignee: Lucent Technologies, Inc.Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang